本文实现了从 Mentor 原理图导出到 AD 的整体流程。因为在原理图设计阶段，想把mentor的原理图导成AD的版本 往往有很多的困难，所以专门写了这篇文档。希望可以指导开发工作。
2021-09-02 11:04:43
551KB
1
MENTOR GRAPHICS UVM/OVM DOCUMENTATION
VERIFICATION METHODOLOGY ONLINE COOKBOOK
Table of Contents
Articles
Introduction
Cookbook/Introduction
Cookbook/Acknowledgements
Testbench Architecture
Testbench/Overview
Testbench/Build
Testbench/Blocklevel
Testbench/IntegrationLevel
Component
Agent
Phasing/Overview
Factory
UsingFactoryOverrides
SystemVerilogPackages
Connections to DUT Interfaces
Connect/Dut Interface
SVCreationOrder
Connect/SystemVerilogTechniques
ParameterizedTests
Connect/Virtual Interface
Config/VirtInterfaceConfigDb
Connect/VirtInterfacePackage
Connect/VirtInterfaceConfigPkg
Connect/TwoKingdomsFactory
VirtInterfaceFunctionCallChain
BusFunctionalModels
ProtocolModules
Connect/AbstractConcrete
Connect/AbstractConcreteConfigDB
Configuring a Test Environment
Config/Overview
Resources/config db
Config/Params Package
Config/ConfiguringSequences
ResourceAccessForSequences
MacroCostBenefit
Analysis Components & Techniques
Analysis/Overview
AnalysisPort
AnalysisConnections
MonitorComponent
Predictors
Scoreboards
CoverageCollectors
CoverageModelSwap
MetricAnalyzers
PostRunPhases
End Of Test Mechanisms
EOT/Overview
Objections
Sequences
Sequences/Overview
Sequences/Items
Transaction/Methods
Sequences/API
Connect/Sequencer
Driver/Sequence API
Sequences/Generation
Sequences/Overrides
Sequences/Virtual
Sequences/Hierarchy
Driver/Use Models
Driver/Unidirectional
Driver/Bidirectional
Driver/Pipelined
Sequences/Arbitration
Sequences/Priority
Sequences/LockGrab
Stimulus/Signal Wait
Stimulus/Interrupts
Sequences/Stopping
Sequences/Layering
Register Abstraction Layer
Registers/Overview
Registers/Specification
Registers/Adapter
Registers/Integrating
Registers/Integration
Registers/Register
2021-08-03 16:35:53
9.13MB
1
Mentor Graphics携手安捷伦发布EDA综合解决方案，RF-PCB开发周期有望缩短一半.pdf
2021-07-25 11:03:53
54KB
mentor官方关于uvm的手册，适合IC验证工程师学习研究和查阅
2021-07-16 11:55:39
708KB
1