【Mentor Graphics官方出品】UVM/OVM Online Methodology Cookbook

MENTOR GRAPHICS UVM/OVM DOCUMENTATION VERIFICATION METHODOLOGY ONLINE COOKBOOK Table of Contents Articles Introduction Cookbook/Introduction Cookbook/Acknowledgements Testbench Architecture Testbench/Overview Testbench/Build Testbench/Blocklevel Testbench/IntegrationLevel Component Agent Phasing/Overview Factory UsingFactoryOverrides SystemVerilogPackages Connections to DUT Interfaces Connect/Dut Interface SVCreationOrder Connect/SystemVerilogTechniques ParameterizedTests Connect/Virtual Interface Config/VirtInterfaceConfigDb Connect/VirtInterfacePackage Connect/VirtInterfaceConfigPkg Connect/TwoKingdomsFactory VirtInterfaceFunctionCallChain BusFunctionalModels ProtocolModules Connect/AbstractConcrete Connect/AbstractConcreteConfigDB Configuring a Test Environment Config/Overview Resources/config db Config/Params Package Config/ConfiguringSequences ResourceAccessForSequences MacroCostBenefit Analysis Components & Techniques Analysis/Overview AnalysisPort AnalysisConnections MonitorComponent Predictors Scoreboards CoverageCollectors CoverageModelSwap MetricAnalyzers PostRunPhases End Of Test Mechanisms EOT/Overview Objections Sequences Sequences/Overview Sequences/Items Transaction/Methods Sequences/API Connect/Sequencer Driver/Sequence API Sequences/Generation Sequences/Overrides Sequences/Virtual Sequences/Hierarchy Driver/Use Models Driver/Unidirectional Driver/Bidirectional Driver/Pipelined Sequences/Arbitration Sequences/Priority Sequences/LockGrab Stimulus/Signal Wait Stimulus/Interrupts Sequences/Stopping Sequences/Layering Register Abstraction Layer Registers/Overview Registers/Specification Registers/Adapter Registers/Integrating Registers/Integration Registers/Register