第六版的计算机组成原理：软件硬件接口。

"1_TO_4 " contains the following sections. 1 VERILOG Examples This section contains the VERILOG examples of Chapter 11 of the book. It supports computer aided searching and own simulations. 2 Interpreter Model This is the complete VERILOG model of the RISC processor TOOBSIE on the behavior level. It serves as a reference for the instruction set. 3 Coarse Structure Model This is the complete VERILOG model of the RISC processor TOOBSIE on the register transfer level and below. 4 Operating System and Examples The operating system VOS supports more comfortable experiments with the Coarse Structure Model. For this purpose, there are also example application programs. This section, however, does not belong to the actual target of the book. "5VWELDOS.ZIP" and "6VWELSUN.ZIP" contain the VERILOG simulator VeriWell for the PC under MS-DOS and the SUN Sparc under UNIX, respectively, as well as our first hints "5_0READ.1ST" and "6_0READ.1ST", respectively, followed by the documentation of the supplier of VeriWell.

在自己的ZYNQ板卡上成功移植了蜂鸟的E203，可以通过调试器连接进行程序下载，可以通过软件控制串口的打印

I2C的学习报告，描述了I2Cmaster和slave的原理和设计思路。

VerilogHDL程序都是我们自己为教学目的而编写的，全部程序在CADENCE公司的LWB (Logic Work Bench)环境下和 Mentor 公司的ModelSim 环境下用Verilog语言进行了仿真, 通过了运行测试，并分别用Synergy和Synplify综合器针对不同的FPGA进行了综合。分别用Xilinx和Altera公司的的布局布线工具在Xilinx3098上和Altera Flex10K10实现了布线。 顺利通过综合前仿真、门级结构仿真以及布线后的门级仿真。这个 CPU 模型只是一个教学模型, 设计也不一定合理, 只是从原理上说明了一个简单的RISC _CPU的构成。

RISC-V内核MCU相关资料

Computer Organization and Design RISC-V Edition-Slides.pdf

一篇不错的本科论文，仅供参考，资源来自网络

GD32VF103CBT6的定时器中断工程, 使用NucleiStudio打开, 具体参考我的博客: GD32VF103_定时器中断

根据Github上的项目编译的Linux上的标准64位RISC-V嵌入式交叉编译链。