advanced computer architecture mainly about instructions

文档收录了华为首席架构师的所有文档,1.企业架构 1.1 企业架构起源和发展 介绍TOGAF的爸爸和爷爷 TOGAF Next Now is the Time for Third Generation EA Methods 1.2 主要企业架构框架 如何选择合适的企业架构框架 EAP发明者Spewak对EAP和Zachman Framework的比较 Enterprise Architecture Planning(EAP)方法论的分析 MIT企业架构核心图 延伸阅读企业架构入门系列十五篇 ` 项目管理体系（PMBOK）与TOGAF的比较 1.3 架构设计思想 组织管理的技术—系统工程 系统、架构、企业，关于跨领域研究 自然界物质的系统性 ArchitectedERP-超越ERP 1.4 企业架构核心概念辨析 架构设计术语注解 企业架构设计基础（一） 企业架构设计基础（二） 企业架构核心概念辨析（一） 企业架构核心概念辨析（二） 延伸阅读 好书推荐： 1.5 企业管理与企业架构 商业模式画布案例 MIT CISR 企业运营模式 企业管理诊断的模型-LCS 1.6 企业架构核心组件 1.6.1 架构设计方法 企业架构设计的方法论体系 IBM企业架构方法论（英文） 1.6.2 架构元模型 TOGAF9.1企业架构元模型解析 The Beauty of Metamodel 1.6.3 架构制品分类 架构连续体 (Continuum) 1.6.4 架构设计技巧 企业架构设计技巧-基于能力的业务规划 价值网模型用于战略分析 1.6.5 架构交付物 TOGAF架构需求说明书和架构定义文件详解 2.业务架构 2.1 业务流程建模 业务架构设计-业务流程建模 业务流程建模-BPMN2.0 业务流程建模语言比较：BPMN2.0与EPC（一） 业务流程建模语言比较：BPMN2.0与EPC（二） 业务流程建模语言比较：BPMN2.0 与EPC（三） 业务流程建模语言比较：BPMN 2.0与EPC（四） 2.2 业务组件建模 组件化业务模型（CBM）介绍（一） 组件化业务模型（CBM）介绍（二） 组件化业务模型（CBM）介绍（三） 2.3 领域建模技术 领域驱动建模 从资源，服务到产品建模 延伸阅读 行业业务架构模型 3.云计算与SOA 3.1关于去IOE 老外谈去IOE，最终可能会回到IOE的怀抱 谈谈去 IOE 运动 Go to IOE，to go or not to go 3.2 云计算架构 云计算开放架构（CCOA） 云计算开放架构应用案例 关于业务流程即服务（BPaaS）交付模式 基于云计算开放架构的业务云（Business Cloud）案例 NIST云计算参考架构 基于云计算平台的信息系统参考架构 3.3 软件即服务（SaaS）架构设计 Force.com平台总体架构（元数据驱动的架构） Force.com平台的数据定义和存储 Force.com多租户架构设计演讲视频 3.4 SOA 3.4.1服务计算介绍 服务计算介绍 服务计算知识体系 3.4.2 服务导向架构设计 服务导向架构的迭代设计方法 3.4.3 产品技术 服务总线性能评估 延伸阅读 网格计算死亡与智慧地球诞生的缘由 对于云+端战略的理解 SAP移动平台（3.0）产品架构 4.数据架构（大数据） 4.1.分布式计算和存储技术 4.1.1算法与数据结构 一致哈希—分布式存储的基础算法 索引原理：布尔代数和搜索引擎的索引 MySQL索引背后的数据结构和算法原理 4.1.2 NoSQL 集群环境下关系型数据库扩展性的问题 数据模型与存储模型的矛盾 NoSQL的来源、主要特征和适用场景 4.1.3分布式文件系统 Google分布式文件系统（GFS） Google分布式计算框架（MR） Google Bigtable Database 4.2大数据应用 对企业大数据应用的理解 大数据流式计算技术解析之一 大数据流式计算技术解析之二 延伸阅读 JamesHamilton的演讲和论文 从CAP定理看设计哲学 5.架构治理 企业架构治理 企业内EA领导团队的建制 数据治理标准体系-DAMA MIT企业架构成熟度模型 企业架构实施绩效的七个度量指标 7 Key Enterprise Architecture Metrics 延伸阅读业务与IT，如何一起快乐的玩耍 6.架构实践 温彻斯特神秘屋-非企业架构设计案例 华为98年IT策略与规划（ITS&P）报告解读 一提盒可乐的价值流 谈业务、流程、IT、质量、运营的关系 美的与华为流程架构领先实践 互联网公司的企业架构实践 美国和亚洲发达国家的企业架构实践 7.企业架构读物 Enterprise Architecture As Strategy—前言 Enterprise Architecture as Strategy 战略执行，首先构建运营基础 Enterprise Architecture as Strategy 你的企业是否有良好的运营基础？ EnterpriseArchitecture as Strategy 如何建立运营基础？ EnterpriseArchitecture as Strategy导读 服务计算经典书籍：Service Computing 推荐几本企业架构英文读物 JeanneRoss介绍企业架构研究（视频） 8.杂文 如何组织会议 阅读的技巧 科技工作者如何做技术交流PPT 谈谈敏捷开发和管理 基础教育的价值-计算机科学与技术

《Clean Architecture: A Craftsman’s Guide to Software Structure and Design》是著名作家Robert C. Martin最新著作，顧名思義這本書的主題就是軟體架構。

Contents About This Book The MindShare Architecture Series.......................................................................................1 Organization of This Book.......................................................................................................2 Who Should Read This Book ..................................................................................................3 Prerequisite Knowledge...........................................................................................................4 Documentation Conventions...................................................................................................4 Hex Notation.......................................................................................................................4 Binary Notation....................................................................................................................4 Decimal Notation.................................................................................................................4 Signal Name Representation..............................................................................................5 Identification of Bit Fields...................................................................................................5 We Want Your Feedback ..........................................................................................................5 E-Mail/Phone/FAX ............................................................................................................5 Bulletin Board.......................................................................................................................6 Mailing Address ..................................................................................................................6 Chapter 1: 80486 Overview System Performance Prior to the 80486..................................................................................7 The Memory Bottleneck ...........................................................................................................7 The Static Ram, or SRAM, Solution...................................................................................8 The External Cache Solution ..............................................................................................8 Advantage: Reduces Many Memory Accesses to Zero Wait States.......................8 Disadvantage: Memory Accesses Still Bound By Bus Speed..................................8 The 80486 Solution: Internal Code/Data Cache ..............................................................9 Faster Memory Accesses..............................................................................................9 Frees Up the Bus...........................................................................................................9 The Floating-Point Bottleneck ................................................................................................9 The 80386/80387 Solution ................................................................................................10 The 80486 Solution: Integrate the FPU............................................................................10 The 80486 Microarchitecture..................................................................................................10 The Intel Family of 486 Processors .......................................................................................12 80486 System Architecture vi Chapter 2: Functional Units The 80486 Functional Units....................................................................................................13 Introduction.......................................................................................................................13 The 80486 Bus Unit............................................................................................................15 The 80486 Cache Unit........................................................................................................15 The Instruction Pipeline/Decode Unit ...........................................................................16 Instruction Prefetch ....................................................................................................17 Two-Stage Instruction Decode..................................................................................18 Execution .....................................................................................................................18 Register Write-Back....................................................................................................18 The Control Unit ................................................................................................................18 The Floating-Point Unit ....................................................................................................19 The Datapath Unit .............................................................................................................19 The Memory Management Unit (MMU)........................................................................20 Chapter 3: The Hardware Interface Hardware Interface..................................................................................................................21 General ...............................................................................................................................21 Clock .........................................................................................................................................23 Address.....................................................................................................................................23 Data Bus....................................................................................................................................24 Data Bus Parity.........................................................................................................................25 Bus Cycle Definition...............................................................................................................26 Bus Cycle Control ....................................................................................................................27 Burst Control ............................................................................................................................28 Interrupts..................................................................................................................................28 Bus Arbitration........................................................................................................................29 Cache Invalidation ..................................................................................................................30 Cache Control ...........................................................................................................................30 Numeric Error Reporting........................................................................................................32 Bus Size Control.......................................................................................................................32 Address Mask...........................................................................................................................33 SL Technology.........................................................................................................................33 Boundary Scan Interface ........................................................................................................34 Upgrade Processor Support ...................................................................................................35 Chapter 4: The 486 Cache and Line Fill Operations The 486 Caching Solution ......................................................................................................37 The 486 Internal Cache......................................................................................................37 The Advantage of a Level 2 Cache..................................................................................38 The 486 with an L2 Look-Through Cache ...........................................................................38 Contents vii Handling of I/O Reads .....................................................................................................40 Handling of I/O Writes ....................................................................................................40 Handling of Memory Reads.............................................................................................40 Handling of Memory Writes ............................................................................................41 Handling of Memory Reads by Another Bus Master ...................................................41 When a Write-Through Policy is Used ....................................................................42 When a Write-Back Policy is Used...........................................................................42 Handling of Memory Writes by Another Bus Master ..................................................42 When a Write-Through Policy is Used ....................................................................43 When a Write-Back Policy is Used...........................................................................43 The Bus Snooping Process .....................................................................................................45 Summary of the L2 Look-Through Cache Designs ...........................................................45 The 486 with an L2 Look-Aside Cache ................................................................................46 Anatomy of a Memory Read..................................................................................................48 The Internal Cache's View of Main Memory .................................................................48 L1 Memory Read Request ................................................................................................49 The Structure of the L1 Cache Controller.......................................................................49 Set the Cache Stage............................................................................................................50 The Cache Look-Up...........................................................................................................52 The Bus Cycle Request ......................................................................................................52 Memory Subsystem Agrees to Perform a Line Fill .......................................................54 Cache Line Fill Defined.....................................................................................................55 Conversion to a Cache Line Fill Operation ....................................................................56 L2 Cache's Interpretation of the Memory Address .......................................................56 The L2 Cache Look-Up .....................................................................................................57 The Affect of the L2 Cache Read Miss on the Microprocessor ....................................57 Organization of the DRAM Main Memory....................................................................57 The Cache Line Fill Transfer Sequence...........................................................................58 The First Doubleword Is Read from DRAM Memory ..................................................59 First Doubleword Transferred to the L2 Cache and the 80486 Microprocessor .................................................................................................59 Memory Subsystem's Treatment of the Next Three Doubleword Addresses ....................................................................................................60 Transfer of the Second Doubleword to the Microprocessor ........................................60 Memory Subsystem Latching of the Third and Fourth Doublewords .......................61 Transfer of the Third Doubleword..................................................................................61 The Beginning of the End .................................................................................................62 Transfer of the Fourth and Final Doubleword...............................................................62 Internal Cache Update ......................................................................................................62 Summary of the Memory Read........................................................................................64 Burst Transfers from Four-Way Interleaved Memory ......................................................64 Burst Transfers from L2 Cache..............................................................................................66 80486 System Architecture viii The Interrupted Burst .............................................................................................................67 Cache Line Fill Without Bursting.........................................................................................69 Internal Cache Handling of Memory Writes......................................................................73 Invalidation Cycles (486 Cache Snooping) .........................................................................73 L1 and L2 Cache Control ........................................................................................................74 Chapter 5: Bus Transactions (Non-Cache) Overview of 486 Bus Cycles...................................................................................................77 Bus Cycle Definition...............................................................................................................78 Interrupt Acknowledge Bus Cycle .......................................................................................79 Special Cycles..........................................................................................................................79 Shutdown Special Cycle ...................................................................................................80 Flush Special Cycle............................................................................................................80 Halt Special Cycle..............................................................................................................80 Stop Grant Acknowledge .................................................................................................81 Write-Back Special Cycle ..................................................................................................81 Non-Burst Bus Cycles .............................................................................................................81 Transfers with 8-,16-, and 32-bit Devices ............................................................................82 Address Translation..........................................................................................................82 Data Bus Steering...............................................................................................................84 Non-Cacheable Burst Reads ..................................................................................................85 Non-Cacheable Burst Writes .................................................................................................87 Locked Transfers......................................................................................................................89 Pseudo-Locked Transfers .......................................................................................................89 Transactions and BOFF# (Bus Cycle Restart) .....................................................................90 The Bus Cycle State Machine................................................................................................91 I/O Recovery Time...................................................................................................................92 Write Buffers ............................................................................................................................93 General ...............................................................................................................................93 The Write Buffers and I/O Cycles...................................................................................94 Chapter 6: SL Technology Introduction to SL Technology Used in the 486 Processors.............................................95 System Management Mode (SMM) .....................................................................................96 System Management Memory (SMRAM)......................................................................98 The SMRAM Address Map.......................................................................................98 Initializing SMRAM.................................................................................................101 Changing the SMRAM Base Address....................................................................101 Entering SMM..................................................................................................................101 The System Asserts SMI ..........................................................................................101 Back-to-Back SMI Requests..............................................................................102 SMI and Cache Coherency...............................................................................102 Contents ix Pending Writes are Flushed to System Memory..................................................102 SMIACT# is Asserted (SMRAM Accessed)...........................................................103 Processor Saves Its State ..........................................................................................103 Auto-HALT Restart...........................................................................................105 SMM Revision Identifier ..................................................................................105 SMBASE Slot ......................................................................................................106 I/O Instruction Restart .....................................................................................106 The Processor Enters SMM .....................................................................................107 Address Space...........................................................................................................108 Exceptions and Interrupts .......................................................................................108 Executing the SMI Handler ............................................................................................109 Exiting SMM.....................................................................................................................109 Processor’s Response to RSM..................................................................................109 State Save Area Restored.........................................................................................110 Maintaining Cache Coherency When SMRAM is Cacheable.............................111 486 Clock Control...................................................................................................................111 The Stop Grant State........................................................................................................111 Stop Clock State ...............................................................................................................113 Auto-HALT Power Down ..............................................................................................113 Stop Clock Snoop State ...................................................................................................114 Chapter 7: Summary of Software Changes Changes to the Software Environment..............................................................................115 Instruction Set Enhancements.............................................................................................116 The Register Set .....................................................................................................................117 Base Architecture Registers............................................................................................117 The System-Level Registers............................................................................................119 Control Register 0 (CR0)..........................................................................................120 Cache Disable (CD) and Not Write-Through (NW) .....................................121 Alignment Mask (AM)......................................................................................121 Write-Protect (WP) ............................................................................................122 Numeric Exception (NE) ..................................................................................122 Control Register 2 (CR2)..........................................................................................122 Control Register 3 (CR3)..........................................................................................123 Control Register 4 (CR4)..........................................................................................123 Global Descriptor Table Register (GDTR).............................................................124 Interrupt Descriptor Table Register (IDTR) ..........................................................124 Task State Segment Register (TR)...........................................................................124 Local Descriptor Table Register (LDTR)................................................................124 Virtual Paging ..................................................................................................................125 The Floating-Point Registers ...................................................................................126 The Debug and Test Registers ................................................................................128 80486 System Architecture x Chapter 8: The 486SX and 487SX Processors Introduction to the 80486SX and 80487SX Processors.....................................................131 The 486SX Signal Interface ..................................................................................................132 Register Differences..............................................................................................................132 Chapter 9: The 486DX2 and 486SX2 Processors The Clock Doubler Processors ............................................................................................135 Chapter 10: The Write Back Enhanced 486DX2 Introduction to the Write Back Enhanced 486DX2 ..........................................................137 Advantage of the Write-Back Policy ..................................................................................138 The Write-Through Policy..............................................................................................138 The Write-Back Policy.....................................................................................................139 Signal Interface ......................................................................................................................139 New Signals......................................................................................................................139 Existing Signals with Modified Functionality..............................................................141 The MESI Model....................................................................................................................141 Write Back Enhanced 486DX2 System without an L2 Cache.........................................144 Cache Line Fill..................................................................................................................144 Bus Master Read — Processor Snoop ...........................................................................146 Bus Master Write — Processor Snoop ..........................................................................148 Write Back Enhanced 486DX2 System with an L2 Cache...............................................150 The L2 Cache with a Write-Through Policy.................................................................151 The L2 Cache with a Write-Back Policy........................................................................152 Snoop Cycle During Cache Line Fill .............................................................................152 Special Cycles.........................................................................................................................155 Clock Control.........................................................................................................................156 Chapter 11: The 486DX4 Processor Primary Feature of the 486DX4 Processor .........................................................................159 Clock Multiplier ....................................................................................................................159 16KB Internal Cache..............................................................................................................160 5vdc Tolerant Design ............................................................................................................162 Glossary..................................................................................................................................165 Index........................................................................................................................................183 Figures xi Figure 1-1. Subsystems Integrated into the 80486 ................................................................ 11 Figure 2-1. 80486 Microarchitecture ....................................................................................... 14 Figure 2-2. The Elements Comprising the 80486 Bus Unit .................................................. 16 Figure 2-3. 80486 Instruction Pipeline.................................................................................... 17 Figure 3-1. 80486 Pin Designations......................................................................................... 22 Figure 4-1. The 486 Processor with an L2 Look-Through cache........................................ 39 Figure 4-2. The 80486 with a Look-Aside External Cache................................................... 47 Figure 4-3. The Structure of the L1 Cache ............................................................................. 51 Figure 4-4. Internal Cache Interpretation of the Memory Address.................................... 52 Figure 4-5. Memory Address at the Start of the Bus Cycle ................................................. 53 Figure 4-6. Cache Line Fill with Bursting .............................................................................. 54 Figure 4-7. 64-Bit Interleaved Memory Architecture ........................................................... 58 Figure 4-8. The LRU Algorithm .............................................................................................. 63 Figure 4-9. 4-way Interleaved Memory Designed to Support Burst Transfers. ............... 65 Figure 4-10. Burst Timing from 4-way Interleaved Memory............................................. 66 Figure 4-11. Burst Timing from L2 Cache.............................................................................. 67 Figure 4-12. The Interrupted Burst......................................................................................... 69 Figure 4-13. Non-Burst Cache Line Fill.................................................................................. 72 Figure 4-14. Cache Invalidation Cycle ................................................................................... 74 Figure 5-1. Example of Non-Burst Cycle Timing.................................................................. 82 Figure 5-2. Address Translation for 8, 16, and 32-bit Devices ............................................ 83 Figure 5-3. System Logic Used to Perform Data Bus Steering............................................ 84 Figure 5-4. Non-Cacheable Burst Read Bus Cycle................................................................ 86 Figure 5-5. Non-Cacheable Burst Write Bus Cycle............................................................... 88 Figure 5-6. 80486 Bus Cycle States.......................................................................................... 91 Figure 6-1. Address Space Available to Processor when Operating in Different Modes................................................................................................. 97 Figure 6-2. Sample Layout of SMM Memory........................................................................ 99 Figure 6-3. Typical PC Memory Map (SMM Disabled versus SMM Enabled)................. 100 Figure 6-4. The Processor’s SMM State-Save Map ............................................................... 104 Figure 6-5. SMM Revision Identifier Definition ................................................................... 105 Figure 6-6. Stop Clock State Diagram .................................................................................... 112 Figure 7-1. The BSWAP Instruction........................................................................................ 117 Figure 7-2. 80486 Base Architecture Registers ...................................................................... 118 Figure 7-3. 486 EFlags Register Definition............................................................................. 119 Figure 7-4. 80486 System Registers......................................................................................... 120 Figure 7-5. Bit definition for CR0............................................................................................ 121 Figure 7-6. Format of CR3........................................................................................................ 123 Figure 7-7. Format of CR4........................................................................................................ 124 Figure 7-8. The 80486 Floating-Point Registers..................................................................... 128 Figure 7-9. The 80486 Debug and Test Registers .................................................................. 129 80486 System Architecture xii Figure 10-1. Example of System with Write Back Enhanced 486DX2 (no L2 Cache)............................................................................................................................ 145 Figure 10-2. Example Cache Line Fill — Write-Back Mode Enabled................................. 146 Figure 10-3. External Snoop Performed by Enhanced Write Back 486DX2 Processor ..................................................................................................................... 149 Figure 10-4. Write Back Enhanced 486 with Look-Through L2 Cache.............................. 150 Figure 10-5. Cache Line Fill with External Snoop ................................................................ 154 Figure 10-6. Stop Clock State Machine for Enhanced Bus Mode ....................................... 156 Figure 11-1. Organization of the 486DX4 Internal Cache.................................................... 161

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