是本人的一门实验课程课题，通过要求，精心写的一份报告，内附vhdl代码，和模块分析

Quartus 中 fft ip core 的中文使用说明，包含ＶＨＤＬ程序代码

该手册非常清楚详尽，据此能使用Quartus中的FFT软核，从而Altera公司的FPGA可以很轻易地实现FFT.

#首先安装Quartus II 11.0软件（默认是32/64-Bit一起安装)： #用Quartus_II_11.0_x86破解器(内部版).exe破解 C:\altera\11.0\quartus\bin下的sys_cpt.dll文件（运行Quartus_II_11.0_x86破解器(内部版).exe后,直接点击“应用补丁”，如果出现“未找到该文件。搜索该文件吗？”，点击“是”，（如果直接把该破解器Copy到 C:\altera\11.0\quartus\bin下，就不会出现这个对话框，而是直接开始破解！）然后选中sys_cpt.dll，点击“打开”。安装默认的sys_cpt.dll路径是在C:\altera\11.0\quartus\bin下）。 #把license.dat里的XXXXXXXXXXXX 用您老的网卡号替换(在Quartus II 11.0的Tools菜单下选择License Setup，下面就有NIC ID)。 #在Quartus II 11.0的Tools菜单下选择License Setup，然后选择License file，最后点击OK。 #注意：license文件存放的路径名称不能包含汉字和空格，空格可以用下划线代替。 #备注：此软件在Windows XP和Windows 7的32/64位操作系统下都验证过了，没有问题！Windows Vista 32/64因为微软都放弃了，所以没有验证，理论上应该可以正常使用。 #仅限于学习,不要用于商业目的! 严禁贴到网上！！！ #此软件已经通过了诺顿测试，在其它某些杀毒软件下，也许被误认为是“病毒”，这是杀毒软件智能化程度不够的原因，所以只能暂时关闭之。

Cyclone2 FPGA读写SRAM IS61LV25616 实验Verilog逻辑源码Quartus工程文件 module SRAM_TEST ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; //output inout [15:0] SRAM_DQ , output reg [17:0] SRAM_ADDR , output reg SRAM_CE , output reg SRAM_OE , output reg SRAM_WE , output reg SRAM_UB , output reg SRAM_LB , output reg [ 7:0] LED ); //Reg define reg [3:0] div_cnt ; reg sram_clk ; reg [5:0] ctrl_cnt ; reg [15:0] sram_data_lck ; reg [15:0] sram_din ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to sram ctrl clk 50M/16 always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 4'b0; else div_cnt <= div_cnt + 4'b1; end //gen sram_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) sram_clk <= 1'b0 ; else if ( div_cnt <= 4'd7 ) sram_clk <= 1'b1 ; else sram_clk <= 1'b0 ; end // sram ctrl signal gen // ctrl_cnt 0 - 31 is for write ctrl // ctrl_cnt 31 - 63 is for read ctrl always @(posedge sram_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ctrl_cnt <= 6'b0; else ctrl_cnt <= ctrl_cnt + 6'b1; end always @(posedge sram_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) SRAM_ADDR <= 18'b0; else if ( ctrl_cnt

Cyclone2 FPGA读写FLASH SST39VF1601 实验Verilog逻辑源码Quartus工程文件 module FLASH_TEST ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; //output inout [15:0] FLASH_DQ , output reg [20:0] FLASH_ADDR , output reg FLASH_CE , output reg FLASH_OE , output reg FLASH_WE , output reg FLASH_RST , output reg [ 7:0] LED ); //Reg define reg [3:0] div_cnt ; reg flash_clk ; reg [31:0] wait_cnt ; reg [5:0] ctrl_cnt ; reg [15:0] flash_data_lck ; reg [15:0] flash_din ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to flash ctrl clk 50M/16 , one flash ctrl clk cycle is 330ns always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 4'b0; else div_cnt <= div_cnt + 4'b1; end //gen flash_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) flash_clk <= 1'b0 ; else if ( div_cnt <= 4'd7 ) flash_clk <= 1'b1 ; else flash_clk <= 1'b0 ; end // flash ctrl signal gen // read FLASH devid need 5 step : // ctrl_cnt 10 - 13 is write oxaa in addr 0x5555 // ctrl_cnt 14 - 17 is write ox55 in addr 0x2aaa // ctrl_cnt 18 - 21 is write ox90 in addr 0x5555 // ctrl_cnt 22 -30 is wait time for TIDA // ctrl_cnt 31 -34 is read manId in addr 0 // ctrl_cnt 35 -38 is read devid in addr

Cyclone2 FPGA读写DAC_TLC5620实验Verilog逻辑源码Quartus工程文件 module DA_TLC5620 ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; //output output reg DA_IO_CLK , output reg DA_LOAD , output reg DA_LDAC , output reg DA_OUT_DATA , output reg [7:0] LED ); //Reg define reg [6:0] div_cnt ; reg da_clk ; reg [4:0] ctrl_cnt ; reg [15:0] delay_cnt ; reg [ 7:0] analog_data ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to da ctrl clk 50M/64 = 0.78Mhz always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 6'b0; else div_cnt <= div_cnt + 6'b1; end //gen da_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) da_clk <= 1'b0 ; else if ( div_cnt <= 6'd31 ) da_clk <= 1'b1 ; else da_clk <= 1'b0 ; end // da ctrl signal gen // ctrl_cnt 0 - 32 is for da ctrl always @(posedge da_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ctrl_cnt <= 5'b0; else ctrl_cnt <= ctrl_cnt + 5'b1; end always @(posedge da_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) DA_IO_CLK <= 1'b0; else if ( ctrl_cnt == 5'd6 || ctrl_cnt == 5'd8 || ctrl_cnt == 5'd10 || ctrl_cnt == 5'd12 || ctrl_cnt == 5'd14 || ctrl_cnt == 5'd16 || ctrl_cnt == 5'd18 || ctrl_cnt == 5'd20 || ctrl_cnt == 5'd22 || ctrl_

Cyclone4 FPGA读写高速AD-TLC549+DA-AD9708模块实验Verilog逻辑源码Quartus工程+文档资料 module DA_AD9708_BASE ( //input input sys_clk , //system clock; // input sys_rst_n , //system reset, low is active; input [3:0] key , //output output reg [7:0] DA_DATA , output reg DA_CLK , output reg [7:0] LED ); //Reg define reg [7:0] div_cnt ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ assign sys_rst_n = 1'b1 ; // counter used for div osc clk to ad ctrl clk 50M/4 = 12.5Mhz always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 8'b0; else div_cnt <= div_cnt + 8'b1; end //gen DA_CLK always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) DA_CLK <= 1'b0 ; else if ( div_cnt == 8'd0 ) DA_CLK <= ~DA_CLK ; else ; end //display AD sample data to LED always @(posedge DA_CLK or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) DA_DATA <= 8'b0; else DA_DATA <= { key, key }; end //display AD sample data to LED always @(posedge DA_CLK or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) LED <= 8'b0; else LED <= { key, key } ; end

Cyclone2 FPGA读写 ADC_TLC549实验Verilog逻辑源码Quartus工程文件, module AD_TLC549 ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; input AD_IO_DATA , //output output reg AD_IO_CLK , output reg AD_CS , output reg [7:0] LED ); //Reg define reg [6:0] div_cnt ; reg ad_clk ; reg [4:0] ctrl_cnt ; reg [7:0] ad_data_shift ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to ad ctrl clk 50M/64 = 0.78Mhz always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 6'b0; else div_cnt <= div_cnt + 6'b1; end //gen ad_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ad_clk <= 1'b0 ; else if ( div_cnt <= 6'd31 ) ad_clk <= 1'b1 ; else ad_clk <= 1'b0 ; end // ad ctrl signal gen // ctrl_cnt 0 - 32is for ad ctrl always @(posedge ad_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ctrl_cnt <= 5'b0; else ctrl_cnt <= ctrl_cnt + 5'b1; end always @(posedge ad_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) AD_IO_CLK <= 1'b0; else if ( ctrl_cnt == 5'd6 || ctrl_cnt == 5'd8 || ctrl_cnt == 5'd10 || ctrl_cnt == 5'd12 || ctrl_cnt == 5'd14 || ctrl_cnt == 5'd16 || ctrl_cnt == 5'd18 || ctrl_cnt == 5'd20 ) // ad clk low AD_IO_CLK <= 1'b1; else AD_IO_CLK <= 1'b0; end always @(posedge ad_clk or negedge sys_rst

Nios_II_PIO的详解与双向操作注意点,，精品分析教程