Cyclone2 FPGA读写SRAM IS61LV25616 实验Verilog逻辑源码Quartus工程文件.zip
Cyclone2 FPGA读写SRAM IS61LV25616 实验Verilog逻辑源码Quartus工程文件
module SRAM_TEST (
//input
input sys_clk , //system clock;
input sys_rst_n , //system reset, low is active;
//output
inout [15:0] SRAM_DQ ,
output reg [17:0] SRAM_ADDR ,
output reg SRAM_CE ,
output reg SRAM_OE ,
output reg SRAM_WE ,
output reg SRAM_UB ,
output reg SRAM_LB ,
output reg [ 7:0] LED
);
//Reg define
reg [3:0] div_cnt ;
reg sram_clk ;
reg [5:0] ctrl_cnt ;
reg [15:0] sram_data_lck ;
reg [15:0] sram_din ;
//Wire define
//************************************************************************************
//** Main Program
//**
//************************************************************************************
// counter used for div osc clk to sram ctrl clk 50M/16
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
div_cnt <= 4'b0;
else
div_cnt <= div_cnt + 4'b1;
end
//gen sram_clk
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
sram_clk <= 1'b0 ;
else if ( div_cnt <= 4'd7 )
sram_clk <= 1'b1 ;
else
sram_clk <= 1'b0 ;
end
// sram ctrl signal gen
// ctrl_cnt 0 - 31 is for write ctrl
// ctrl_cnt 31 - 63 is for read ctrl
always @(posedge sram_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
ctrl_cnt <= 6'b0;
else
ctrl_cnt <= ctrl_cnt + 6'b1;
end
always @(posedge sram_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
SRAM_ADDR <= 18'b0;
else if ( ctrl_cnt
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本站所有资源不代表本站的观点或立场，基于网友分享，根据中国法律《信息网络传播权保护条例》第二十二条之规定，若资源存在侵权或相关问题请联系本站客服人员，zhiweidada#qq.com，请把#换成@，本站将给予最大的支持与配合，做到及时反馈和处理。关于更多版权及免责申明参见 版权及免责申明