Cyclone2 FPGA读写DAC_TLC5620实验Verilog逻辑源码Quartus工程文件.zip

Cyclone2 FPGA读写DAC_TLC5620实验Verilog逻辑源码Quartus工程文件 module DA_TLC5620 ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; //output output reg DA_IO_CLK , output reg DA_LOAD , output reg DA_LDAC , output reg DA_OUT_DATA , output reg [7:0] LED ); //Reg define reg [6:0] div_cnt ; reg da_clk ; reg [4:0] ctrl_cnt ; reg [15:0] delay_cnt ; reg [ 7:0] analog_data ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to da ctrl clk 50M/64 = 0.78Mhz always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 6'b0; else div_cnt <= div_cnt + 6'b1; end //gen da_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) da_clk <= 1'b0 ; else if ( div_cnt <= 6'd31 ) da_clk <= 1'b1 ; else da_clk <= 1'b0 ; end // da ctrl signal gen // ctrl_cnt 0 - 32 is for da ctrl always @(posedge da_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ctrl_cnt <= 5'b0; else ctrl_cnt <= ctrl_cnt + 5'b1; end always @(posedge da_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) DA_IO_CLK <= 1'b0; else if ( ctrl_cnt == 5'd6 || ctrl_cnt == 5'd8 || ctrl_cnt == 5'd10 || ctrl_cnt == 5'd12 || ctrl_cnt == 5'd14 || ctrl_cnt == 5'd16 || ctrl_cnt == 5'd18 || ctrl_cnt == 5'd20 || ctrl_cnt == 5'd22 || ctrl_