THE CONTEXT OF PARALLEL PROCESSING The field of digital computer architecture has grown explosively in the past two decades. Through a steady stream of experimental research, tool-building efforts, and theoretical studies, the design of an instruction-set architecture, once considered an art, has been transformed into one of the most quantitative branches of computer technology. At the same time, better understanding of various forms of concurrency, from standard pipelining to massive parallelism, and invention of architectural structures to support a reasonably efficient and user-friendly programming model for such systems, has allowed hardware performance to continue its exponential growth. This trend is expected to continue in the near future. This explosive growth, linked with the expectation that performance will continue its exponential rise with each new generation of hardware and that (in stark contrast to software) computer hardware will function correctly as soon as it comes off the assembly line, has its down side. It has led to unprecedented hardware complexity and almost intolerable dev- opment costs. The challenge facing current and future computer designers is to institute simplicity where we now have complexity; to use fundamental theories being developed in this area to gain performance and ease-of-use benefits from simpler circuits; to understand the interplay between technological capabilities and limitations, on the one hand, and design decisions based on user and application requirements on the other.

Volume 1: Describes the architecture and programming environment of processors supporting IA-32 and Intel® 64 architectures. Volume 2: Includes the full instruction set reference, A-Z. Describes the format of the instruction and provides reference pages for instructions. Volume 3: Includes the full system programming guide, parts 1, 2, 3, and 4. Describes the operating-system support environment of Intel® 64 and IA-32 architectures, including: memory management, protection, task management, interrupt and exception handling, multi-processor support, thermal and power management features, debugging, performance monitoring, system management mode, virtual machine extensions (VMX) instructions, Intel® Virtualization Technology (Intel® VT), and Intel® Software Guard Extensions (Intel® SGX). Volume 4: Describes the model-specific registers of processors supporting IA-32 and Intel® 64 architectures.

Communication Networks Fundamental Concepts and Key Architectures Alberto Leon-Garcia & Indra Widjaja

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.

VLSI Test Principles and Architectures Design for Testability 集成电路测试经典教材 清华老师推荐

Frequency Diverse Array Receiver Architectures 讲FDA的比较完整的电子书

AMD开发者手册2020年最新版 官网可以免费下载，我这里只是打包在一起 包换1-5单卷 AMD64 Architecture Programmer’s Manual Volume 1(Application Programming).pdf AMD64 Architecture Programmer’s Manual Volume 2(System Programming).pdf AMD64 Architecture Programmer’s Manual Volume 3(General Purpose and System Instructions).pdf AMD64 Architecture Programmer’s Manual Volume 4(128-bit and 256 bit media instructions).pdf AMD64 Architecture Programmer’s Manual Volume 5(64-Bit Media and x87 Floating-Point Instructions).pdf 以及合集 AMD64 Architecture Programmer’s Manual Volumes 1-5.pdf

Optimizing Compilers for Modern Architectures.pdf

This book addresses researchers and graduate students at the forefront of study/research on the Internet of Things (IoT) by presenting state-of-the-art research together with the current and future challenges in building new smart applications (e.g., Smart Cities, Smart Buildings, and Industrial IoT) in an efficient, scalable, and sustainable way. It covers the main pillars of the IoT world (Connectivity, Interoperability, Discoverability, and Security/Privacy), providing a comprehensive look at the current technologies, procedures, and architectures.

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