搜索【uvm】的结果

代码在书里有，其中注释是我自己加的，对应博文里的讲解。

2021-08-05 20:03:13 47KB UVM 数字IC验证

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【Mentor Graphics官方出品】UVM/OVM Online Methodology Cookbook

MENTOR GRAPHICS UVM/OVM DOCUMENTATION VERIFICATION METHODOLOGY ONLINE COOKBOOK Table of Contents Articles Introduction Cookbook/Introduction Cookbook/Acknowledgements Testbench Architecture Testbench/Overview Testbench/Build Testbench/Blocklevel Testbench/IntegrationLevel Component Agent Phasing/Overview Factory UsingFactoryOverrides SystemVerilogPackages Connections to DUT Interfaces Connect/Dut Interface SVCreationOrder Connect/SystemVerilogTechniques ParameterizedTests Connect/Virtual Interface Config/VirtInterfaceConfigDb Connect/VirtInterfacePackage Connect/VirtInterfaceConfigPkg Connect/TwoKingdomsFactory VirtInterfaceFunctionCallChain BusFunctionalModels ProtocolModules Connect/AbstractConcrete Connect/AbstractConcreteConfigDB Configuring a Test Environment Config/Overview Resources/config db Config/Params Package Config/ConfiguringSequences ResourceAccessForSequences MacroCostBenefit Analysis Components & Techniques Analysis/Overview AnalysisPort AnalysisConnections MonitorComponent Predictors Scoreboards CoverageCollectors CoverageModelSwap MetricAnalyzers PostRunPhases End Of Test Mechanisms EOT/Overview Objections Sequences Sequences/Overview Sequences/Items Transaction/Methods Sequences/API Connect/Sequencer Driver/Sequence API Sequences/Generation Sequences/Overrides Sequences/Virtual Sequences/Hierarchy Driver/Use Models Driver/Unidirectional Driver/Bidirectional Driver/Pipelined Sequences/Arbitration Sequences/Priority Sequences/LockGrab Stimulus/Signal Wait Stimulus/Interrupts Sequences/Stopping Sequences/Layering Register Abstraction Layer Registers/Overview Registers/Specification Registers/Adapter Registers/Integrating Registers/Integration Registers/Register

2021-08-03 16:35:53 9.13MB UVM OVM Verification Methodology

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V2.2_UVM_ABC.7z

2021-08-03 09:09:40 313KB dsd scsas

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最新的SV IEEE 1800-2017 和 UVM IEEE 1800.2-2017英文版

最新的SV IEEE 1800-2017 和 UVM IEEE 1800.2-2017英文版，适合从事半导体行业的设计和验证工程师参考，ieee 权威文档，包含system verilog 和UVM 两个电子版的资料，文档齐全。

2021-08-02 15:21:21 11.09MB systemverilog UVM 验证设计

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SystemVerilog Verification UVM 1.1 Lab Guide

SystemVerilog Verification UVM 1.1 Lab Guide.pdf

2021-07-30 15:53:07 30.98MB uvm 1.1 lab guide

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uvm class book，能够提供uvm类的定义

uvm class book，能够提供uvm类的定义，标准的uvm开发包，一本好书

2021-07-25 21:22:57 2.65MB uvm 类定义接口

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win10_questasim_uvm_sim.zip

基于win10平台的questasim仿真 uvm验证环境

2021-07-23 09:02:38 12.21MB win10questasim uvm验证平台

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A-Practical-Guide-to-Adopting-the-Universal-Verification-Methodology(UVM).pdf

the-Universal-Verification-Methodology(UVM)验证的介绍书籍，可作为SV验证知道。。。。。。。。。。。。。。。。

2021-07-23 08:55:57 3.72MB system verilog SV UVM

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Systemverilog+UVM搭建SOC

svUVM搭建利用Systemverilog+UVM搭建SOC及ASIC的RTL验证环境

2021-07-21 10:31:23 2.93MB UVM实战

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a practical guide to adopting the universal verification methodology中文版.pdf

中文版UVM验证方法学的详细讲解，包含UVM的各大工作机制，诸如factory机制、phase机制、config_db机制等等，此外还含有一些较为详细的源代码讲解，是验证方法学的必备参考书

2021-07-19 22:54:40 5.84MB UVM

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