目前最经典的IC验证相关的systemverilog书籍，没有之一
2021-05-08 16:25:29
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简单的uart verilog源码，没有奇偶校验位，1bit停止位，8bit数据位，MSB先。实际测试通过。可在此基础上修改自己需要的uart源码
2021-04-30 11:07:30
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VE-2016-1009，OpenSSH版本过低，处理的方案【https://blog.csdn.net/qq_15088653/article/details/116264275】，pam-devel-1.1.8-23.el7.x86_64.rpm、libopenssl-devel-1.0.1c-2.1.3.x86_64.rpm、zlib-devel-1.2.7-2.1.2.x86_64.rpm、openssl-1.0.2h.tar.gz、openssh-7.4p1.tar.gz
2021-04-29 14:00:15
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二维DCT的Verilog实现，包含算法基础，模块设计等所需知识。The application note describes a 2 dimensional DCT function implemented on a Xilinx FPGA. Behavioral code is provided for the implementation on any Xilinx device. Some of the advantageous of the module includes parametrizeability and performance guarantee. The code can be further optimized by instantiating embedded adders and multipliers when targeting Virtex2 family. After an initial latency of 92 clock cycles, one DCT value is output at every clock.
2021-04-28 18:54:54
64KB
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