[{"title":"( 15 个子文件 269KB ) Verilog 语言设计单周期MIPS CPU(42条指令)","children":[{"title":"MIPS CPU设计实验报告.doc <span style='color:#111;'> 453.50KB </span>","children":null,"spread":false},{"title":"mips_cpu","children":[{"title":"Test_42_Instr.dat <span style='color:#111;'> 860B </span>","children":null,"spread":false},{"title":"ctrl_encode_def.v <span style='color:#111;'> 706B </span>","children":null,"spread":false},{"title":"sccomp_tb(1).v <span style='color:#111;'> 2.81KB </span>","children":null,"spread":false},{"title":"EXT.v <span style='color:#111;'> 244B </span>","children":null,"spread":false},{"title":"ctrl.v <span style='color:#111;'> 6.57KB </span>","children":null,"spread":false},{"title":"dm.v <span style='color:#111;'> 2.62KB </span>","children":null,"spread":false},{"title":"NPC.v <span style='color:#111;'> 703B </span>","children":null,"spread":false},{"title":"mux.v <span style='color:#111;'> 2.39KB </span>","children":null,"spread":false},{"title":"PC.v <span style='color:#111;'> 288B </span>","children":null,"spread":false},{"title":"sccpu.v <span style='color:#111;'> 4.10KB </span>","children":null,"spread":false},{"title":"RF.v <span style='color:#111;'> 1.30KB </span>","children":null,"spread":false},{"title":"alu.v <span style='color:#111;'> 2.09KB </span>","children":null,"spread":false},{"title":"im.v <span style='color:#111;'> 170B </span>","children":null,"spread":false},{"title":"sccomp.v <span style='color:#111;'> 1.65KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]