Altium Designer的常用的库3M Actel Agilent Technologies Altera等

AD 原理图 设计任务： 设计并制作一个具有编码、译码功能的电路，并显示译码结果。 一、设计要求 1、可以对“0”,“1”,“2”……“9“十个按键进行编码。 2、可以译码，并用七段数码管显示出来

AD pcb布局电路 设计任务： 设计并制作一个具有编码、译码功能的电路，并显示译码结果。 一、设计要求 1、可以对“0”,“1”,“2”……“9“十个按键进行编码。 2、可以译码，并用七段数码管显示出来

详细介绍了matlab APP 的设计，包括GUI设计，代码生成，与硬件结合，MVC模式等，还是比较好的一个matlab设计参考资料。

Altium Designer 14中文版标准实例教程 [王明秋，胡仁喜 编著] 2015年版.pdf。

The Verilog Hardware Description Language (Verilog-HDL) has long been the most popular language for describing complex digital hardware. It started life as a proprietary language but was donated by Cadence Design Systems to the design community to serve as the basis of an open standard. That standard was formalized in 1995 by the IEEE in standard 1364-1995. About that same time a group named Analog Verilog International formed with the intent of proposing extensions to Verilog to support analog and mixed-signal simulation. The first fruits of the labor of that group became available in 1996 when the language definition of Verilog-A was released. Verilog-A was not intended to work directly with Verilog-HDL. Rather it was a language with Similar syntax and related semantics that was intended to model analog systems and be compatible with SPICE-class circuit simulation engines. The first implementation of Verilog-A soon followed: a version from Cadence that ran on their Spectre circuit simulator.

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数字时钟电路（数字电路设计）文件内包含数字时钟电路原理图、PCB板、3D封装。 数字电路设计，采用逻辑门电路，CD4511译码器，CD4518计数器等其他外围电路构成。

通过 App Designer 进行基本 Simulink 参数控制的介绍。

Altium Designer的3D元件库，包括原理图库，封装库，自己做智能车的时候用的，比较全。