很好的中文版UVM指南。根据这个可以直接写出一个较为复杂的UVM testbench了。

UVM入门进阶实验testbeach

I2C的testbeach平台

UVM实战 用TB写的testbeach

包含SystemVerilog的图书SystemVerilog for Verification（第3版）以及最新版IEEE标准；SystemVerilog Assertions的图书A Practical Guide for SystemVerilog Assertions；UVM1.2源码、官方手册、最新版IEEE标准以及图书A practical guide to adopting the universal verfication methodology(UVM)。

一个简单的uvm笔试题

自己实测后整理的uvm_phase顺序 自己实测后整理的uvm_phase顺序

Verification has evolved into a complex project that often spans internal and external teams, but the discontinuity associated with multiple, incompatible methodologies among those teams has limited productivity. The Universal Verification Methodology (UVM) 1.1 Class Reference addresses verification complexity and interoperability within companies and throughout the electronics industry for both novice and advanced teams while also providing consistency. While UVM is revolutionary, being the first verification methodology to be standardized, it is also evolutionary, as it is built on the Open Verification Methodology (OVM), which combined the Advanced Verification Methodology (AVM) with the Universal Reuse Methodology (URM) and concepts from the e Reuse Methodology (eRM). Furthermore, UVM also infuses concepts and code from the Verification Methodology Manual (VMM), plus the collective experience and knowledge of the 300+ members of the Accellera Verification IP Technical Subcommittee (VIP-TSC) to help standardize verification methodology.

UVM的学习PPT

一个简单的uvm+makefile验证环境，解压之后可直接运行