使用 Vivado HLS 和 AXI4-Stream 实现拉普拉斯滤波器示例。 您可以使用 GIMP2 以 RAW 格式查看结果。 原始图像大小为 240x120 像素（输出为 solution1/csim/build/image.data）。 结果图像大小为 238x118 像素（输出为 solution1/csim/build/result.data）。 原来的： 输出： 数据流： 请注意，只需要 2 个行缓冲区。 另请参阅：par2pix 分支，它的速度提高了 2 倍。

资料很多课程，FPGA vivado zynq 教程 例程

Vivado Reed-Solomon Encoder License License，不需要绑定MAC地址，最高权限Source IP，永久有效，Vivado2999之前版本都能使用。

vivado 2015.4 软件下载

博客配套：https://blog.csdn.net/botao_li/article/details/85257566

BITS-Vivado：我学习Vivado和HLS的经验

VIVADO的CDMA设计实例，主要是arm还有fpga之间的axi_acp通信

Mentor, a Siemens business, has unveiled ModelSim 10.7, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment. About Mentor Graphics ModelSim. Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused. In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code. The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).

VIVADO从此开始_高亚军编著 2017讲述Xilinx Vivado的书。

Vivado可以将自己的verilog代码设计封装成IP，然后在设计中调用该ip.ip还可以配置参数。所用软件为2014.4