非线性连续系统安全性验证的启发式方法
2021-02-25 17:05:24 387KB System Safety Verification Barrier
1
The paper outline a framework to analyze and verify both the runtime safety and the functional correctness of Solidity contracts in F*, a functional programming language aimed at program verification.
2021-01-28 05:07:10 291KB 智能合约 形式验证
1
一本学UVM很好的,我自己就是看着这本书入门的, 希望对大家有帮助。
2020-03-04 03:06:12 3.72MB UVM
1
Logic Synthesis and Verification Algorithms
2020-02-01 03:08:21 39.81MB logic
1
并发程序的验证方法和基础.对于编写并行程序、并行程序测试、程序正确性验证等方面的同学值得一看
2020-01-27 03:07:52 2.53MB verification
1
ystemverilog for verification second edition 源代码 源代码
2020-01-15 03:02:34 28KB systemverilog  verification 源代码
1
Writing Testbenches,Functional Verification of HDL Models.pdf
2020-01-03 11:26:50 12.98MB Writing Testbenches
1
1 Verifi cation Guidelines ........................................................................... 1 1.1 The Verifi cation Process ................................................................ 2 1.1.1 Testing at Different Levels ............................................... 3 1.1.2 The Verifi cation Plan ........................................................ 4 1.2 The Verifi cation Methodology Manual .......................................... 4 1.3 Basic Testbench Functionality ....................................................... 5 1.4 Directed Testing ............................................................................. 5 1.5 Methodology Basics ...................................................................... 6 1.6 Constrained-Random Stimulus ...................................................... 8 1.7 What Should You Randomize? ...................................................... 9 1.7.1 Device and Environment Confi guration ........................... 9 1.7.2 Input Data ......................................................................... 10 1.7.3 Protocol Exceptions, Errors, and Violations .................... 10 1.7.4 Delays and Synchronization ............................................. 11 1.7.5 Parallel Random Testing .................................................. 11 1.8 Functional Coverage ...................................................................... 12 1.8.1 Feedback from Functional Coverage to Stimulus ............ 12 1.9 Testbench Components .................................................................. 13 1.10 Layered Testbench ......................................................................... 14 1.10.1 A Flat Testbench .............................................................. 14 1.10.2 The Signal and Command Layers .................................... 17 1.10.3 The Functional Layer ....................................................... 17 1.10.4 The Scenario Layer .........................
2019-12-21 22:15:13 10.01MB Verilog
1
UVM介绍的很详细,未来验证方法学的发展趋势,希望对你有用
2019-12-21 22:13:18 12.19MB UVM 验证方法学
1
本人学习过程中整理的各项UVM相关资料,包括:UVM primer, UVM实战及笔记,UVM Cookbook,SV_UVM_Debug,UVM初级开发指南,UVM快速学习教程等。
2019-12-21 22:02:17 36.08MB UVM SV Verification
1