現在高速介面流行的coding技術，用在PCIE和USB3

Xilinx 8B/10B Xilinx and its licensors make and you receive no warranties or conditions, express, implied, statutory or otherwise, and Xilinx specifically disclaims any implied warranties of merchantability

%8b%a8测管理系统与拨测终端设备接口要求

包括两个阶段：元胞自动机置乱阶段、阴影生成阶段； 目前程序已成功运行，内置图片除lena之外为已运行结果。

一篇讲解8B/10B编码的硕士论文，写的比较全面

用于JESD204B中的编码技术，详细描述了8B/10B编码的技术原理和方法，以及相应的verilog代码，对于理解编码技术非常有用，对于设计基于JESD204B接口的serdes十分有用

光纤通信8b 10源代码 verilog实现 解码编码等各个模块

8B_Unit3_Online_tours_单元检测卷(含答案).pdf

8B_Unit8_A_green_world单元综合卷(B)及答案.pdf

When most system designers look at serializer/deserializer (SerDes) devices, they often compare speed and power without considering how the SerDes works and what it actually does with their data. Internal SerDes architecture may seem irrelevant, but this overlooked item can dictate many important system parameters like system topology, protocol overhead, data formatting and flow, latency, clocking and timing requirements, and the need for additional buffering as well as logic. These issues can have a big impact on system cost, performance, and efficiency.