FPGA控制LCD12864显示屏显示图片实验Verilog逻辑源码Quartus11.0工程文件, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。 ​ module LCD12864(clk,rst,lcd12864_rs,lcd12864_rw,lcd12864_en,lcd12864_data,psb); input clk; //系统时钟 input rst; //复位信号 output lcd12864_rs; //1:数据模式;0:指令模式 output lcd12864_rw; //1:读操作;0:写操作 output lcd12864_en; //使能信号,写操作时在下降沿将数据送出;读操作时保持高电平 output psb; output[7:0] lcd12864_data; //LCD数据总线 reg lcd12864_rs; reg lcd12864_en; reg[7:0] lcd12864_data; reg[3:0] state; //状态机 reg[3:0] next_state; reg[14:0] div_cnt; //分频计数器 reg[9:0] cnt; //写操作计数器 reg cnt_rst; //写操作计数器复位信号 wire[7:0] data; //要显示的数据 reg clk_div; //分频时钟 /********************状态机参数*********************/ parameter idle = 4'b0000, setbase_1 = 4'b0001, setmode_1 = 4'b0010, setcurs_1 = 4'b0111, setexte_1 = 4'b0100, setexte_2 = 4'b1100, wr_y_addr_1 = 4'b1101, wr_y_addr_2 = 4'b1111, wr_x_addr_1 = 4'b1110, wr_x_addr_2 = 4'b1010, wr_data_1 = 4'b1011, wr_data_2 = 4'b1001; assign lcd12864_rw = 1'b0; //对LCD始终为写操作 assign psb=1'b1; //开背光灯 /******************时钟分频**********************/ always @(posedge clk or negedge rst) begin if(!rst) div_cnt <= 15'd0; else if(div_cnt==15'h4000) begin div_cnt <= 15'd0; clk_div<=~clk_div; end else div_cnt <= div_cnt+ 1'b1; end /**************状态机转向*********/ always @(posedge clk_div or negedge rst) begin if(!rst) state <= idle; else state <= next_state; end /***************************************************************/

FPGA控制LCD12864显示屏显示4行字符实验Verilog逻辑源码Quartus11.0工程文件，, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。 module lcd12864(clk,rs,rw,en,dat,psb); input clk; //系统时钟输入50M output [7:0] dat; //LCD的8位数据口 output rs,rw,en,psb; //LCD的控制脚 reg e; reg [7:0] dat; reg rs; reg [15:0] counter; reg [6:0] current,next; reg clkr; reg [1:0] cnt; ///////////////////////////////////////////// assign psb=1'b1; assign rw=0; always @(posedge clk) //da de shi zhong pinlv begin counter=counter+1; if(counter==16'h000f) clkr=~clkr; end //////////////////////////////////////////////// always @(posedge clkr) begin current=next; case(current) 7'd0: begin rs<=0; dat<=8'h31; next<=next+1'b1;end //*设置8位格式,* 7'd1: begin rs<=0; dat<=8'h0C; next<=next+1'b1;end //*整体显示,关光标,不闪烁*/ 7'd2: begin rs<=0; dat<=8'h06; next<=next+1'b1; end //*设定输入方式,增量不移位*/ 7'd3: begin rs<=0; dat<=8'h01; next<=next+1'b1; end //*清除显示*/ 7'd4: begin rs<=1; dat<=8'hB4; next<=next+1'b1; end //显示第一行 7'd5: begin rs<=1; dat<=8'hF3; next<=next+1'b1; end 7'd6: begin rs<=1; dat<=8'hCE; next<=next+1'b1; end 7'd7: begin rs<=1; dat<=8'hF7;next<=next+1'b1; end 7'd8: begin rs<=1; dat<=8'hB9; next<=next+1'b1; end 7'd9: begin rs<=1; dat<=8'hCF; next<=next+1'b1; end 7'd10: begin rs<=1; dat<="-"; next<=next+1'b1; end 7'd11: begin rs<=1; dat<="F";next<=next+1'b1; end 7'd12: begin rs<=1; dat<="P"; next<=next+1'b1; end 7'd13: begin rs<=1; dat<="G";next<=next+1'b1; end 7'd14: begin rs<=1; dat<="A"; next<=next+1'b1; end 7'd15: begin rs<=1; dat<="!"; next<=next+1'b1; end 7'd16: begin