FPGA控制LCD12864显示屏显示4行字符实验Verilog逻辑源码Quartus11.0工程文件.zip

FPGA控制LCD12864显示屏显示4行字符实验Verilog逻辑源码Quartus11.0工程文件，, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。 module lcd12864(clk,rs,rw,en,dat,psb); input clk; //系统时钟输入50M output [7:0] dat; //LCD的8位数据口 output rs,rw,en,psb; //LCD的控制脚 reg e; reg [7:0] dat; reg rs; reg [15:0] counter; reg [6:0] current,next; reg clkr; reg [1:0] cnt; ///////////////////////////////////////////// assign psb=1'b1; assign rw=0; always @(posedge clk) //da de shi zhong pinlv begin counter=counter+1; if(counter==16'h000f) clkr=~clkr; end //////////////////////////////////////////////// always @(posedge clkr) begin current=next; case(current) 7'd0: begin rs<=0; dat<=8'h31; next<=next+1'b1;end //*设置8位格式,* 7'd1: begin rs<=0; dat<=8'h0C; next<=next+1'b1;end //*整体显示,关光标,不闪烁*/ 7'd2: begin rs<=0; dat<=8'h06; next<=next+1'b1; end //*设定输入方式,增量不移位*/ 7'd3: begin rs<=0; dat<=8'h01; next<=next+1'b1; end //*清除显示*/ 7'd4: begin rs<=1; dat<=8'hB4; next<=next+1'b1; end //显示第一行 7'd5: begin rs<=1; dat<=8'hF3; next<=next+1'b1; end 7'd6: begin rs<=1; dat<=8'hCE; next<=next+1'b1; end 7'd7: begin rs<=1; dat<=8'hF7;next<=next+1'b1; end 7'd8: begin rs<=1; dat<=8'hB9; next<=next+1'b1; end 7'd9: begin rs<=1; dat<=8'hCF; next<=next+1'b1; end 7'd10: begin rs<=1; dat<="-"; next<=next+1'b1; end 7'd11: begin rs<=1; dat<="F";next<=next+1'b1; end 7'd12: begin rs<=1; dat<="P"; next<=next+1'b1; end 7'd13: begin rs<=1; dat<="G";next<=next+1'b1; end 7'd14: begin rs<=1; dat<="A"; next<=next+1'b1; end 7'd15: begin rs<=1; dat<="!"; next<=next+1'b1; end 7'd16: begin