定浮点数转换程序(verilog)

上传者: zagly | 上传时间: 2023-02-14 16:50:24 | 文件大小: 4.63MB | 文件类型: RAR
a) 并采用门级编程,实现4-bit无符号整数到浮点数转换; b) 并采用RTL级编程,实现4-bit无符号整数到浮点数转换; c) 分别对门级编程实现和RTL级编程实现的组合逻辑电路进行功能仿真; d) 利用“实验板”对两种4-bit无符号整数到浮点数转换电路进行综合和实现,设定定点数输入和浮点数输出的人机接口,建议用4个LED灯表示输入值,操作开关或按动按钮后进行转换,用数码管显示有效位和幂指数;(任何合理的人机接口都是可以接受的)

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