串并转换与并串转换的Verilog实现

上传者: reggae25 | 上传时间: 2019-12-21 20:59:45 | 文件大小: 332KB | 文件类型: zip
quartus环境下工程,自己写的sipo和piso两个模块,用verilog分别实现串并转换和并串转换,通俗易懂

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评论信息

  • 不爱吃蘑菇的兔子 :
    不知道能不能用
    2018-11-27

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