Verilog课程设计-自动售货机

四、程序代码段 module autoseller(clk,g,m,yes,read,zero,led_dig,led_seg,led_c,led_r,led); input clk,yes,read,zero;//确定键，商家读取键，清零键 input [3:0] g , m; //货品及投币选择键 output led_dig,led_seg,led_c,led_r,led;//数码管输出及点阵输出 reg f_100;//分频时钟 reg f_1; reg [3:0] goods,money,led,change,g_c; integer r,a,b, a_tmp2,a_tmp1; integer ret=0;//用于控制各状态间的转换 reg [9:0]count; reg [7:0] led_c,led_r,led_dig,led_seg; reg [1:0]state; integer i; reg x; always @ (posedge clk) //分频模块 begin if(a_tmp2==999) begin f_100=~f_100; a_tmp2<=0; end else a_tmp2<=a_tmp2+1; end always @ (posedge clk) begin if(a_tmp1==9999999) begin f_1=~f_1; a_tmp1<=0; end else a_tmp1<=a_tmp1+1; end always @ (posedge f_1) begin if(ret!=0) //用于按确认键后的计时 begin a=a+1; end else begin