基于altera FPGA 的 UART IP核

[{"title":"（ 356 个子文件 1.48MB ） 基于altera FPGA 的 UART IP核","children":[{"title":"uart_transmitter.v <span style='color:#111;'> 9.55KB </span>","children":null,"spread":false},{"title":"uart_top.v <span style='color:#111;'> 6.60KB </span>","children":null,"spread":false},{"title":"uart_fifo.v <span style='color:#111;'> 9.67KB </span>","children":null,"spread":false},{"title":"uart_receiver.v <span style='color:#111;'> 12.25KB </span>","children":null,"spread":false},{"title":"uart_defines.v <span style='color:#111;'> 7.55KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]