[{"title":"( 5 个子文件 2.14MB ) verilog语法规则和模板.rar","children":[{"title":"语法模板","children":[{"title":"tb.v <span style='color:#111;'> 1.76KB </span>","children":null,"spread":false},{"title":"bitslip_ctrl.v <span style='color:#111;'> 3.16KB </span>","children":null,"spread":false},{"title":"usrt_master.v <span style='color:#111;'> 15.26KB </span>","children":null,"spread":false},{"title":"Verilog语言编程规范.docx <span style='color:#111;'> 2.14MB </span>","children":null,"spread":false},{"title":"scan_reg.v <span style='color:#111;'> 10.67KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]