[{"title":"( 152 个子文件 7.72MB ) 【EDA】Timer计时器Verilog及testbench","children":[{"title":"FakeCPU.v <span style='color:#111;'> 856B </span>","children":null,"spread":false},{"title":"sim.v <span style='color:#111;'> 1.40KB </span>","children":null,"spread":false},{"title":"MONITOR.v <span style='color:#111;'> 600B </span>","children":null,"spread":false},{"title":"Waveform.vwf <span style='color:#111;'> 13.33KB </span>","children":null,"spread":false},{"title":"sim.v.bak <span style='color:#111;'> 1.39KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]