DDC相关的VerilogHDL源代码，希望对大家有用

16位乘法器VerilogHDL源代码，适合于初学者

利用Xilinx的Vivado套件（包括VivadoHLS）设计的精简指令集CPU架构，里面包含了各个模块所需的仿真文件。下载资源的人需要先了解一下ARM指令集与ARM架构。

用verilog写的密码锁，在quartusII上仿真成功

数字电路设计实验PROJECT 音乐播放器verilog HDL,通过验收

该文档里包含verilog语言编写的双线性插值实现图像缩放的算法

Michael D. Ciletti的这本书时高级进阶教程，掌握高级设计方法必备

quartus ii verilog hdl 正弦信号发生器 附生成mif文件的cpp源码

FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain. Using a FIFO to pass data from one clock domain to another clock domain requires multi-asynchronous clock design techniques. There are many ways to design a FIFO wrong. There are many ways to design a FIFO right but still make it difficult to properly synthesize and analyze the design. This paper will detail one method that is used to design, synthesize and analyze a safe FIFO between different clock domains using Gray code pointers that are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions. The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style #1) is included.

用VERILOG HDL语言设计频率为1HZ的交通灯，分为主干道、辅干道，分别有红、绿、黄、左转灯、黄灯循环显示，各灯显示时间不同。