使用Quartcs II 环境编用Verilog HDL写的交通灯程序

--rtl 这是源代码 --sim 这是modelsim仿真目录 已经验证，可以实现异步FIFO 两级寄存器实现读写指针的同步，地址采用格雷码形式防止亚稳态。异步FIFO的源码，个人觉得不易理解，故上传本人最近写的源码，与大家一起分享

通过jtag为CPLD做软件升级

cpld xc9572xl-vq44 简单系统原理图 pcb pdf格式 cpld简单应用

基于dspC5416开发板上的cpld源代码，很多开发板上都不带的

用CPLD实现单片机与ISA总线接口的并行通信，电路结构简单、体积小，1片CPLD芯片足够，并且控制方便，实时性强，通信效率高。本设计方法已成功地应用于作者开发的各种数据采集系统中，用作单片机与PC104之间的并行数据通信，效果非常理想。

According to the standard IEC 61508 fault insertion testing is required for the verification of fail-safe systems. Usually these systems are realized with microcontrollers. Fail-safe systems based on a novel CPLD-based architecture require a different method to perform fault insertion testing than microcontroller-based systems. This paper describes a method to accomplish fault insertion testing of a system based on the novel CPLD-based architecture using the original system hardware. The goal is to verify the realized safety integrity measures of the system by inserting faults and observing the behavior of the system. The described method exploits the fact, that the system contains two channels, where both channels contain a CPLD. During a test one CPLD is configured using a modified programming file. This file is available after the compilation of a VHDL-description, which was modified using saboteurs or mutants. This allows injecting a fault into this CPLD. The other CPLD is configured as fault-free device. The entire system has to detect the injected fault using its safety integrity measures. Consequently it has to enter and/or maintain a safe state. 微信号：safetyfirst61508

矿渣4205 4203的点灯范例

ise中综合的各个参数的介绍以及配置的说明

xilinx pcie phy 设计介绍