cpld xc9572xl-vq44 简单系统原理图 pcb pdf格式 cpld简单应用
2021-03-05 09:13:52 649KB cpld xc9572xl-vq44 简单系统原理图
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基于dspC5416开发板上的cpld源代码,很多开发板上都不带的
2021-03-04 15:46:46 174KB dspc5416 cpld
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CPLD实现单片机与ISA总线接口的并行通信,电路结构简单、体积小,1片CPLD芯片足够,并且控制方便,实时性强,通信效率高。本设计方法已成功地应用于作者开发的各种数据采集系统中,用作单片机与PC104之间的并行数据通信,效果非常理想。
2021-03-01 09:49:25 145KB CPLD 单片机 ISA总线 并行通信
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According to the standard IEC 61508 fault insertion testing is required for the verification of fail-safe systems. Usually these systems are realized with microcontrollers. Fail-safe systems based on a novel CPLD-based architecture require a different method to perform fault insertion testing than microcontroller-based systems. This paper describes a method to accomplish fault insertion testing of a system based on the novel CPLD-based architecture using the original system hardware. The goal is to verify the realized safety integrity measures of the system by inserting faults and observing the behavior of the system. The described method exploits the fact, that the system contains two channels, where both channels contain a CPLD. During a test one CPLD is configured using a modified programming file. This file is available after the compilation of a VHDL-description, which was modified using saboteurs or mutants. This allows injecting a fault into this CPLD. The other CPLD is configured as fault-free device. The entire system has to detect the injected fault using its safety integrity measures. Consequently it has to enter and/or maintain a safe state. 微信号:safetyfirst61508
2021-02-26 16:00:28 298KB 硬件测试
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矿渣4205 4203的点灯范例
2021-02-26 14:01:15 22.35MB fpga/cpld
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ise中综合的各个参数的介绍以及配置的说明
2021-02-23 12:02:34 457KB 编译器 fpga/cpld
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xilinx pcie phy 设计介绍
2021-02-19 09:05:36 1.31MB pci-e xilinx fpga/cpld
Xilinx Design Constraints(XDC)文件的UltraEdit高亮文件,自己写的,效果可以,语法高亮方面基本上囊括了所有关键字(截至2020.12),但是csdn无法发截图,无法给大家发效果图,有需要的朋友欢迎下载哈(*^_^*),建议采用Ultraedit15及以上版本,15以下版本也可以用,但颜色效果可能会差一点点。
2021-02-17 18:05:40 3KB vivado xilinx fpga/cpld
W77E58 51单片机+CPLD 30路自动测温电路protel 设计硬件原理图PCB设计文件,采用2层板设计,板子大小为151x164mm,双面布局布线,主要器件包括W77E58,EPM7128SLC84-15(84),MAX232,SN7407 ,XTR105 等。Protel 99se 设计的DDB后缀项目工程文件,包括完整无措的原理图及PCB印制板图,可用Protel或 Altium Designer(AD)软件打开或修改,可作为你产品设计的参考。
EPM1270 cpld数据采集板protel 99se设计硬件(原理图PCB bom)+ VERILOG控制逻辑设计工程文件,PCB采用2层板设计,板子大小为80x60mm,双面布局布线,主要器件为EPM1270T144C5,ADM3202,LM2596,TIL191等。 Protel 99se 设计的DDB后缀项目工程文件,包括完整的原理图PCB BOM文件 和VERILOG逻辑工程设计文件(quartus ii 7.2 工程文件),以及设计文档,硬件可用Protel或 Altium Designer(AD)软件打开或修改,已经制板并在实际项目中使用,可作为你产品设计的参考。