PCI_Express_Base_3.0_Specification 一定要收集，官网要会员制才能获得

Section 1. Motivation and Background of PCI Express Section 2. Governing Specifications for the Reference Clock Section 3. History and Objectives of the PCIe Jitter Analysis Methodology Section 4. Overview of PCI Express Jitter Compliance Verification. Section 5. Clock Architectures and Transfer Functions Section 6. Processing Period Data from a Real Time Oscilloscope Section 7. Reference Clock Jitter Specification Limits Section 8. Spread Spectrum Clocking Section 9. HCSL Electrical Specifications Section 10. Interfacing Among Various I/O Standards Section 11. Measurement Tips Section 12. Conclusion Revision History

包括PCI_Express_CEM_r1.1、PCI_Express_CEM_r2.0、PCI_Express_CEM_r3.0、PCI_Express_CEM_r4.0、PCI_Express_CEM_r5.0，一次下载，全部获取。

PCI, PCIe 具体描述见：PCIe资料分享-快速入门 https://blog.csdn.net/BjarneCpp/article/details/80370986

PCI Express System Architecture 222页 PCIE 系统架构，很好的参考资料

本书讲述了与PCI及PCI Express总线相关的最为基础的内容，并介绍了一些必要的、与PCI总线相关的处理器体系结构知识，这也是本书的重点所在。详细讲述了与体系结构相关的PCI Express总线的知识

《PCI Express体系结构导读》书籍影印pdf版本，内容涵盖PCI总线基础知识及PCIe总线体系架构。

PCIe SPEC

'We have always recommended these books to our customers and even our own engineers for developing a better understanding of technologies and specifications. We find the latest PCI Express book from MindShare to have the same content and high quality as all the others.' --Nader Saleh, CEO/President, Catalyst Enterprises, Inc. PCI Express is the third-generation Peripheral Component Inter-connect technology for a wide range of systems and peripheral devices. Incorporating recent advances in high-speed, point-to-point interconnects, PCI Express provides significantly higher performance, reliability, and enhanced capabilities--at a lower cost--than the previous PCI and PCI-X standards. Therefore, anyone working on next-generation PC systems, BIOS and device driver development, and peripheral device design will need to have a thorough understanding of PCI Express. PCI Express System Architecture provides an in-depth description and comprehensive reference to the PCI Express standard. The book contains information needed for design, verification, and test, as well as background information essential for writing low-level BIOS and device drivers.In addition, it offers valuable insight into the technology's evolution and cutting-edge features. Following an overview of the PCI Express architecture, the book moves on to cover transaction protocols, the physical/electrical layer, power management, configuration, and more. Specific topics covered include: *Split transaction protocol *Packet format and definition, including use of each field *ACK/NAK protocol *Traffic Class and Virtual Channel applications and use *Flow control initialization and operation *Error checking mechanisms and reporting options *Switch design issues *Advanced Power Management mechanisms and use *Active State Link power management *Hot Plug design and operation *Message transactions *Physical layer functions *Electrical signaling characteristics and issues *PCI Express enumeration procedures *Configuration register definitions Thoughtfully organized, featuring a plethora of illustrations, and comprehensive in scope, PCI Express System Architecture is an essential resource for anyone working with this important technology.MindShare's PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel. 0321156307B08262003

This paper presents power management guidelines for PCI Express links on Intel-based Mobile platforms. It describes the mapping from platform sleeping states and device power states to link power states, including the procedure to support Mobile-specific S1/POS and CPU C3/C4 scenarios. Device and platform power saving opportunities are identified for each link power state. L1 entry policy is also recommended to optimize device power. Several power optimization techniques are described, including minimizing flow control updates and acknowledgement packets to improve bandwidth efficiency, and pipelining packets to increase opportunities for active state link power management. These power management guidelines enable architectural innovation to achieve power-optimized interconnect performance.