PCI Express Base Specification Revision 2.0 协议规范

1. INTRODUCTION............................................................................................................... 46 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 46 1.2. PCI EXPRESS LINK......................................................................................................... 49 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 50 1.3.1. Root Complex........................................................................................................ 50 1.3.2. Endpoints .............................................................................................................. 51 1.3.3. Switch .................................................................................................................... 54 1.3.4. Root Complex Event Collector .............................................................................. 55 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 55 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 55 1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 56 1.5.1. Transaction Layer ................................................................................................. 57 1.5.2. Data Link Layer .................................................................................................... 57 1.5.3. Physical Layer ...................................................................................................... 58 1.5.4. Layer Functions and Services............................................................................... 58 TRANSACTION LAYER SPECIFICATION ................................................................. 62 2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 62 2.1.1. Address Spaces, Transaction Types, and Usage................................................... 63 2.1.2. Packet Format Overview ...................................................................................... 65 2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 67 2.2.1. Common Packet Header Fields ............................................................................ 67 2.2.2. TLPs with Data Payloads - Rules ......................................................................... 70 2.2.3. TLP Digest Rules .................................................................................................. 74 2.2.4. Routing and Addressing Rules .............................................................................. 74 2.2.5. First/Last DW Byte Enables Rules........................................................................ 78 2.2.6. Transaction Descriptor ......................................................................................... 81 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 87 2.2.8. Message Request Rules ......................................................................................... 94 2.2.9. Completion Rules ................................................................................................ 115 2.2.10. TLP Prefix Rules ................................................................................................. 118 2.3. HANDLING OF RECEIVED TLPS.................................................................................... 123 2.3.1. Request Handling Rules...................................................................................... 126 2.3.2. Completion Handling Rules................................................................................ 138 2.4. TRANSACTION ORDERING ............................................................................................ 142 2.4.1. Transaction Ordering Rules ............................................................................... 142 ......

PCIe3.0协议规范原文件

'We have always recommended these books to our customers and even our own engineers for developing a better understanding of technologies and specifications. We find the latest PCI Express book from MindShare to have the same content and high quality as all the others.' --Nader Saleh, CEO/President, Catalyst Enterprises, Inc. PCI Express is the third-generation Peripheral Component Inter-connect technology for a wide range of systems and peripheral devices. Incorporating recent advances in high-speed, point-to-point interconnect

NVM Express and the PCI Express* SSD RevolutionSSDS003Danny Cobb, CTO Flash Memory Business Unit, EMC Amber Huffman, Sr. Principal Engineer, Intel2Agenda• NVM Express (NVMe) Overview• New NVMe Features in Enterprise & Client• Driver Ecosystem for NVMe• NVMe Interoperability and Plugfest Plans• EMC’s Perspective: NVMe Use Cases and Proof PointsThe PDF for this Session presentation is available from our Technical Session Catalog at the end of the day at:intel.com/go/idfsessions URL is on to

介绍固态硬盘的架构及pcie接口的一本书。 对于ssd的了解有帮助

MindShare_PCI Express Technology 3.0.pdf

M.2接口的详细手册，里面有详细的介绍，包括接插件封装、板卡尺寸等等

PCIE1.0-3.0规范解读，从硬件接口到上层应用，生动而详细的对规范进行了解读；有助于相关从业者对协议进行人如了解，和作为标准协议的导读文本

PICe学习资料，PCI Express System Architecture英文版