英特尔 LPC接口规范，LPC总线，原名叫Low pin count Bus，是在IBM PC兼容机中用于把低带宽设备和“老旧”连接到CPU上。那些常见低速设备有：BIOS，串口，并口，PS/2的键盘和鼠标，软盘控制器，比较新的设备有可信平台模块。LPC总线通常和主板上的南桥物理相连，南桥在IBM PC AT平台上通常连接了一系列的“老旧”设备，例如两个可编程中断控制器， 可编程计时器和两个 ISA DMA 控制器。

I2C-Bus 是一种世界范围的标准，使用广泛。通用的I2C总线被使用在各种控制架构之中，如：系统管理总线(SMBus)、电源管理总线(PMBus)，智能平台管理接口(IPMI)，显示数据通道(DDC)和高级电信计算架构(ATCA)。本文档主要是规范IIC的开发，是学习IIC以及使用IIC的必备参考资料。

Base Device Behavior Specification中文翻译，zigbee3.0 的BDB文档

DP端HDCP2.3 CTS测试说明文档，版本1.1

PCI Express Base Specification Revision 2.0 协议规范

Accessory Interface Specification Release R28 Apple附件接口规范v28，无水印

This specification defines a standardized NAND Flash device interface that provides the means for a system to be designed that supports a range of NAND Flash devices without direct design pre-association. The solution also provides the means for a system to seamlessly make use of new NAND devices that may not have existed at the time that the system was designed.

1.1 Purpose This document, which all other MOST Specifications relate to, is the main specification of MOST (Media Oriented System Transport). 1.2 Scope This document contains the specification of the MOST application layer and the MOST network layer. This specification is speed grade independent. However, it is not fully backward compatible to the existing speed grades MOST25 and MOST50 as described in the MOST Specification Rev. 2.5. In some cases a differentiation between specific implementations (speed grade, physical interface) is necessary. The following terms are used to mark corresponding passages.

1. INTRODUCTION............................................................................................................... 46 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 46 1.2. PCI EXPRESS LINK......................................................................................................... 49 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 50 1.3.1. Root Complex........................................................................................................ 50 1.3.2. Endpoints .............................................................................................................. 51 1.3.3. Switch .................................................................................................................... 54 1.3.4. Root Complex Event Collector .............................................................................. 55 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 55 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 55 1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 56 1.5.1. Transaction Layer ................................................................................................. 57 1.5.2. Data Link Layer .................................................................................................... 57 1.5.3. Physical Layer ...................................................................................................... 58 1.5.4. Layer Functions and Services............................................................................... 58 TRANSACTION LAYER SPECIFICATION ................................................................. 62 2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 62 2.1.1. Address Spaces, Transaction Types, and Usage................................................... 63 2.1.2. Packet Format Overview ...................................................................................... 65 2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 67 2.2.1. Common Packet Header Fields ............................................................................ 67 2.2.2. TLPs with Data Payloads - Rules ......................................................................... 70 2.2.3. TLP Digest Rules .................................................................................................. 74 2.2.4. Routing and Addressing Rules .............................................................................. 74 2.2.5. First/Last DW Byte Enables Rules........................................................................ 78 2.2.6. Transaction Descriptor ......................................................................................... 81 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 87 2.2.8. Message Request Rules ......................................................................................... 94 2.2.9. Completion Rules ................................................................................................ 115 2.2.10. TLP Prefix Rules ................................................................................................. 118 2.3. HANDLING OF RECEIVED TLPS.................................................................................... 123 2.3.1. Request Handling Rules...................................................................................... 126 2.3.2. Completion Handling Rules................................................................................ 138 2.4. TRANSACTION ORDERING ............................................................................................ 142 2.4.1. Transaction Ordering Rules ............................................................................... 142 ......

2019年最新版的NGPON2 PMD层标准 G.989.2，光网络接入的核心技术标准之一，NGPON2光模块主流厂商参考的行业规范：40-Gigabit-capable passive optical networks (NG-PON2): Transmission convergence layer specification。