含异步清0和同步时钟使能的4位加法计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT4B IS
PORT (CLK : IN STD_LOGIC; RST : IN STD_LOGIC;
ENA : IN STD_LOGIC;
OUTY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT : OUT STD_LOGIC );
END CNT4B;
ARCHITECTURE behav OF CNT4B IS
SIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
P_REG: PROCESS(CLK, RST, ENA)
BEGIN
P_REG: PROCESS(CLK, RST, ENA)
BEGIN
IF RST = '1' THEN CQI <= "0000";
ELSIF CLK'EVENT AND CLK = '1' THEN
IF ENA = '1' THEN CQI <= CQI + 1;
ELSE CQI <= "0000";
END IF;
END IF;
OUTY <= CQI ;
END PROCESS P_REG ;
COUT <= CQI(0) AND CQI(1) AND CQI(2) AND CQI(3); --进位输出
END behav;
2021-10-27 08:12:43
2.19MB
VDHL语言
1