SPI的verilog IP核

[{"title":"（ 23 个子文件 562KB ） SPI的verilog IP核","children":[{"title":"simple_spi","children":[{"title":"tags","children":[{"title":"initial","children":[{"title":"rtl","children":[{"title":"verilog","children":[{"title":"fifo4.v <span style='color:#111;'> 4.19KB </span>","children":null,"spread":false},{"title":"simple_spi_top.v <span style='color:#111;'> 9.64KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}],"spread":true},{"title":"branches","children":null,"spread":false},{"title":"web_uploads","children":null,"spread":false},{"title":"trunk","children":[{"title":"rtl","children":[{"title":"verilog","children":[{"title":"fifo4.v <span style='color:#111;'> 4.19KB </span>","children":null,"spread":false},{"title":"simple_spi_top.v <span style='color:#111;'> 10.08KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"sim","children":[{"title":"rtl_sim","children":[{"title":"bin","children":[{"title":"Makefile <span style='color:#111;'> 3.43KB </span>","children":null,"spread":false}],"spread":true},{"title":"run","children":[{"title":"ncvlog.log <span style='color:#111;'> 78B </span>","children":null,"spread":false},{"title":"stdout.log <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"waves","children":[{"title":"waves.do <span style='color:#111;'> 5.09KB </span>","children":null,"spread":false}],"spread":true},{"title":"ncsim.log <span style='color:#111;'> 255B </span>","children":null,"spread":false},{"title":"Makefile <span style='color:#111;'> 3.43KB </span>","children":null,"spread":false},{"title":"simvision.sv <span style='color:#111;'> 14.86KB </span>","children":null,"spread":false},{"title":"ncwork","children":[{"title":"work","children":[{"title":".inca.db.135.linux <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":".inca.db.148.lnx86 <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"inca.lnx86.148.pak <span style='color:#111;'> 1.42MB </span>","children":null,"spread":false},{"title":".cdsvmod <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"inca.linux.135.pak <span style='color:#111;'> 1.20MB </span>","children":null,"spread":false}],"spread":false},{"title":"hdl.var <span style='color:#111;'> 1.05KB </span>","children":null,"spread":false},{"title":"cds.lib <span style='color:#111;'> 57B </span>","children":null,"spread":false}],"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"doc","children":[{"title":"simple_spi.pdf <span style='color:#111;'> 54.03KB </span>","children":null,"spread":false},{"title":"src","children":[{"title":"simple_spi.doc <span style='color:#111;'> 391.50KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"bench","children":[{"title":"verilog","children":[{"title":"spi_slave_model.v <span style='color:#111;'> 3.68KB </span>","children":null,"spread":false},{"title":"wb_master_model.v <span style='color:#111;'> 5.38KB </span>","children":null,"spread":false},{"title":"tst_bench_top.v <span style='color:#111;'> 6.12KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}],"spread":true}],"spread":true}]