[{"title":"( 394 个子文件 29.08MB ) 基于Vivado2018的数字基带信号HDB3编译码完整工程文件,带RAM模拟信道,FIR脉冲成型,可直接testbench仿真","children":[{"title":"vivado_9236.backup.log <span style='color:#111;'> 17.91KB </span>","children":null,"spread":false},{"title":"vivado_1292.backup.log <span style='color:#111;'> 12.83KB </span>","children":null,"spread":false},{"title":"README.txt <span style='color:#111;'> 130B </span>","children":null,"spread":false},{"title":"xbip_utils_v3_0_vh_rfs.vhd <span style='color:#111;'> 178.38KB </span>","children":null,"spread":false},{"title":"fir_compiler_v7_2_vh_rfs.vhd <span style='color:#111;'> 4.10MB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]