verilog 程序实现uart收发

[{"title":"（ 144 个子文件 619KB ） verilog 程序实现uart收发","children":[{"title":"datagene.v.bak <span style='color:#111;'> 1.42KB </span>","children":null,"spread":false},{"title":"uartfifo_assignment_defaults.qdf <span style='color:#111;'> 41.47KB </span>","children":null,"spread":false},{"title":"uartfifo.qsf <span style='color:#111;'> 3.41KB </span>","children":null,"spread":false},{"title":"uartfifo.fit.smsg <span style='color:#111;'> 411B </span>","children":null,"spread":false},{"title":"uartfifo.asm.rpt <span style='color:#111;'> 7.99KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]