MIPS_CU (练习)
在行为VHDL中描述支持以下MIPS ISA子集（即11条指令）的MIPS控制单元（CU）
a) 7 Arithmetic/Logical instructions: add, sub, and, or, nor, slt, addi
b) 2 Memory reference: lw, sw
c) 2 Control transfer: beq, j
所需的MIPS CU的功能，接口和结构如图1所示。CU具有以下接口：
• Generics
- Instruction width (n_bits_instr = instr_mem_width with default value of 32)
- Location of the operation (OP) code least significant bit in the instruction (opcode_start with default value of 26)
- Location of the operation (OP) code most significant bit in the instruction (opcode_end with default value of 31)
- Location of the function (funct) code least significant bit in the instruction (funct_start with default value of 0)
- Location of the function (funct) code most significant bit in the instruction (funct_end with default value of 5)
- Total number of supported ALU operations/functions (n_functions_alu with default value of 16)
• Inputs
- Instruction fetched (Instr -> n_bits_instr bits)
• Outputs
- Register destination (RegDst -> 1 bit)
- Register write enable (RegWrite -> 1 bit)
- ALU source (ALUSrc -> 1 bit)
- ALU control (ALUControl -> [log2 (n_functions_alu)] bits)
- Memory write enable (MemWrite -> 1 bit)
- Memory read enable (MemRead -> 1 bit)
- Memory to register (MemToReg -> 1 bit)
- Conditional branch on equal (BEQ -> 1 bit)
- Unconditional branch (J -> 1 bit)
• In Vivado
- Create a blank project
- Add design and simulation source files
- Run behavioral simulation
- Your waveform configuration should be identical to the provided waveform snapshot, see Figure 2.
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资源详情
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