合创伺服电机整套学习资料:含原理图,源代码(DSP+FPGA)。原理图和代码完整。

上传者: 44723848 | 上传时间: 2023-02-23 14:53:10 | 文件大小: 44.89MB | 文件类型: ZIP
原理图包含200W到2KW的PCB设计,包含控制芯片方案,采样电路,编码器信号处理电路等等,参考学习性极强。源代码包含DSP和FPGA的编写,采用工业级范例编写,可学习和参考性极强。

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[{"title":"( 371 个子文件 44.89MB ) 合创伺服电机整套学习资料:含原理图,源代码(DSP+FPGA)。原理图和代码完整。","children":[{"title":"HCSA_FPGA_S.ldf <span style='color:#111;'> 1.03KB </span>","children":null,"spread":false},{"title":"CLK_75M.lpc <span style='color:#111;'> 1.21KB </span>","children":null,"spread":false},{"title":"CLK_75M.srp <span style='color:#111;'> 1.18KB </span>","children":null,"spread":false},{"title":"CLK_75M_generate.log <span style='color:#111;'> 1.39KB </span>","children":null,"spread":false},{"title":"clk_75m.sym <span style='color:#111;'> 254B </span>","children":null,"spread":false},{"title":"msg_file.log <span style='color:#111;'> 1.24KB </span>","children":null,"spread":false},{"title":"CLK_75M.jhd <span style='color:#111;'> 119B </span>","children":null,"spread":false},{"title":"CLK_75M.ipx <span style='color:#111;'> 546B </span>","children":null,"spread":false},{"title":"CLK_75M.vhd <span style='color:#111;'> 7.93KB </span>","children":null,"spread":false},{"title":"CLK_75M_tmpl.vhd <span style='color:#111;'> 460B </span>","children":null,"spread":false},{"title":"CLK_75M.sort <span style='color:#111;'> 13B </span>","children":null,"spread":false},{"title":"CLK_75M.naf <span style='color:#111;'> 46B </span>","children":null,"spread":false},{"title":".spread_sheet.ini <span style='color:#111;'> 949B </span>","children":null,"spread":false},{"title":"Strategy1.sty <span style='color:#111;'> 291B </span>","children":null,"spread":false},{"title":".floorplanner.ini <span style='color:#111;'> 411B </span>","children":null,"spread":false},{"title":".run_manager.ini <span style='color:#111;'> 927B </span>","children":null,"spread":false},{"title":"reportview.xml <span style='color:#111;'> 476B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S.lpf <span style='color:#111;'> 6.77KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_summary.html <span style='color:#111;'> 5.66KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper.srr <span style='color:#111;'> 78.84KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_premap.szr <span style='color:#111;'> 9.84KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper.szr <span style='color:#111;'> 22.43KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper.srr_Min <span style='color:#111;'> 15.17KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_premap.srr <span style='color:#111;'> 3.39KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_hdl_info_gen_runstatus.xml <span style='color:#111;'> 937B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper_area_report.xml <span style='color:#111;'> 1.05KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_premap_runstatus.xml <span style='color:#111;'> 1.53KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper_resourceusage.rpt <span style='color:#111;'> 629B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper_opt_report.xml <span style='color:#111;'> 1.36KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_premap_errors.txt <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_compiler_notes.txt <span style='color:#111;'> 1.82KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper_errors.txt <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_premap_notes.txt <span style='color:#111;'> 128B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper_gated_clk.rpt <span style='color:#111;'> 34.84KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper_retiming.rpt <span style='color:#111;'> 301B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper_timing_report.xml <span style='color:#111;'> 1.31KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_compiler_warnings.txt <span style='color:#111;'> 1.97KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_compiler_runstatus.xml <span style='color:#111;'> 1.62KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_premap_warnings.txt <span style='color:#111;'> 2.39KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper_runstatus.xml <span style='color:#111;'> 1.55KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper_generated_clk.rpt <span style='color:#111;'> 18.48KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper_warnings.txt <span style='color:#111;'> 2.28KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_fpga_mapper_notes.txt <span style='color:#111;'> 2.04KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_compiler_errors.txt <span style='color:#111;'> 123B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_synplify.html <span style='color:#111;'> 90.60KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.ngd <span style='color:#111;'> 980.86KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.pt <span style='color:#111;'> 36B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.prf <span style='color:#111;'> 3.25KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_synplify.tcl <span style='color:#111;'> 1.89KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_scck.rpt <span style='color:#111;'> 2.17KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.par <span style='color:#111;'> 10.49KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.srs <span style='color:#111;'> 96.67KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_compiler.xdm <span style='color:#111;'> 8.89KB </span>","children":null,"spread":false},{"title":"stdout.log <span style='color:#111;'> 1.93KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_map.cam <span style='color:#111;'> 5.73KB </span>","children":null,"spread":false},{"title":"cmdrec_hdl_info_gen.log <span style='color:#111;'> 1.60KB </span>","children":null,"spread":false},{"title":"hdlorder.tcl <span style='color:#111;'> 298B </span>","children":null,"spread":false},{"title":"cmdrec_compiler.log <span style='color:#111;'> 1.54KB </span>","children":null,"spread":false},{"title":"run_option.xml <span style='color:#111;'> 1.11KB </span>","children":null,"spread":false},{"title":"cmdrec_premap.log <span style='color:#111;'> 2.43KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.plg <span style='color:#111;'> 3.27KB </span>","children":null,"spread":false},{"title":"cmdrec_fpga_mapper.log <span style='color:#111;'> 1.95KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_mapvho.sdf <span style='color:#111;'> 877.31KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_vho.sdf <span style='color:#111;'> 1.00MB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_mapvho.vho <span style='color:#111;'> 6.44MB </span>","children":null,"spread":false},{"title":"reveal_error.log <span style='color:#111;'> 110B </span>","children":null,"spread":false},{"title":"run_options.txt <span style='color:#111;'> 2.02KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.par <span style='color:#111;'> 890B </span>","children":null,"spread":false},{"title":"5_1.ncd <span style='color:#111;'> 1.25MB </span>","children":null,"spread":false},{"title":"5_1.par <span style='color:#111;'> 9.62KB </span>","children":null,"spread":false},{"title":"5_1_par.asd <span style='color:#111;'> 2.90KB </span>","children":null,"spread":false},{"title":"5_1.pad <span style='color:#111;'> 45.39KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.mt <span style='color:#111;'> 33B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_map.ncd <span style='color:#111;'> 820.56KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.srf <span style='color:#111;'> 88.66KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.edi <span style='color:#111;'> 947.91KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.p2t <span style='color:#111;'> 98B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_tw1.html <span style='color:#111;'> 33.41KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_mrp.html <span style='color:#111;'> 35.49KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_synplify.lpf <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.ncd <span style='color:#111;'> 1.25MB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.ngo <span style='color:#111;'> 443.87KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.drc <span style='color:#111;'> 39B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.t2b <span style='color:#111;'> 77B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S.jed <span style='color:#111;'> 490.13KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.srd <span style='color:#111;'> 116.63KB </span>","children":null,"spread":false},{"title":"hcsa_fpga_s_hcsa_fpga_s_trce.asd <span style='color:#111;'> 331B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.srm <span style='color:#111;'> 1021.49KB </span>","children":null,"spread":false},{"title":"hcsa_fpga_s_hcsa_fpga_s.ior <span style='color:#111;'> 14.28KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.areasrr <span style='color:#111;'> 3.16KB </span>","children":null,"spread":false},{"title":"hdldiagram_gen_hierarchy.html <span style='color:#111;'> 9.50KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_bgn.html <span style='color:#111;'> 5.77KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.alt <span style='color:#111;'> 2.66KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.tw1 <span style='color:#111;'> 29.21KB </span>","children":null,"spread":false},{"title":"automake.log <span style='color:#111;'> 5.06KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_ngd.asd <span style='color:#111;'> 21B </span>","children":null,"spread":false},{"title":".build_status <span style='color:#111;'> 3.18KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_iotiming.html <span style='color:#111;'> 16.20KB </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S.p3t <span style='color:#111;'> 116B </span>","children":null,"spread":false},{"title":"HCSA_FPGA_S_HCSA_FPGA_S_pad.html <span style='color:#111;'> 47.36KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]

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