PLD.rar_verilog课件

[{"title":"（ 6 个子文件 5.54MB ） PLD.rar_verilog课件","children":[{"title":"课件","children":[{"title":"第6章Verilog HDL.pdf <span style='color:#111;'> 663.04KB </span>","children":null,"spread":false},{"title":"作业1.pdf <span style='color:#111;'> 58.48KB </span>","children":null,"spread":false},{"title":"第3章 PLD开发工具.pdf <span style='color:#111;'> 1.67MB </span>","children":null,"spread":false},{"title":"第1章 EDA技术与数字系统设计.pdf <span style='color:#111;'> 1.18MB </span>","children":null,"spread":false},{"title":"第2章 FPGA—CPLD.pdf <span style='color:#111;'> 1.78MB </span>","children":null,"spread":false},{"title":"第4-5章Verilog HDL.pdf <span style='color:#111;'> 573.00KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]