jtag_vpi:TCPIP控制的VPI JTAG接口

[{"title":"（ 34 个子文件 75KB ） jtag_vpi:TCPIP控制的VPI JTAG接口","children":[{"title":"jtag_vpi-master","children":[{"title":"jtag_vpi.core <span style='color:#111;'> 786B </span>","children":null,"spread":false},{"title":"jtag_common.c <span style='color:#111;'> 7.66KB </span>","children":null,"spread":false},{"title":"jtag_common.h <span style='color:#111;'> 727B </span>","children":null,"spread":false},{"title":"jtagServer.cpp <span style='color:#111;'> 7.20KB </span>","children":null,"spread":false},{"title":"sim","children":[{"title":"bin","children":[{"title":"Makefile.verilator <span style='color:#111;'> 1.28KB </span>","children":null,"spread":false},{"title":"Makefile <span style='color:#111;'> 1.13KB </span>","children":null,"spread":false}],"spread":true},{"title":"run","children":[{"title":"Makefile <span style='color:#111;'> 243B </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"bench","children":[{"title":"verilog","children":[{"title":"adv_debugsys","children":[{"title":"syncreg.v <span style='color:#111;'> 5.74KB </span>","children":null,"spread":false},{"title":"adbg_jsp_module.v <span style='color:#111;'> 20.69KB </span>","children":null,"spread":false},{"title":"adbg_or1k_status_reg.v <span style='color:#111;'> 6.47KB </span>","children":null,"spread":false},{"title":"syncflop.v <span style='color:#111;'> 4.81KB </span>","children":null,"spread":false},{"title":"adbg_jsp_biu.v <span style='color:#111;'> 16.78KB </span>","children":null,"spread":false},{"title":"adv_dbg_if.v <span style='color:#111;'> 14.98KB </span>","children":null,"spread":false},{"title":"bytefifo.v <span style='color:#111;'> 7.50KB </span>","children":null,"spread":false},{"title":"adbg_wb_biu.v <span style='color:#111;'> 14.07KB </span>","children":null,"spread":false},{"title":"adbg_or1k_module.v <span style='color:#111;'> 28.36KB </span>","children":null,"spread":false},{"title":"adbg_or1k_biu.v <span style='color:#111;'> 9.26KB </span>","children":null,"spread":false},{"title":"adbg_wb_module.v <span style='color:#111;'> 31.22KB </span>","children":null,"spread":false},{"title":"adbg_crc32.v <span style='color:#111;'> 3.86KB </span>","children":null,"spread":false}],"spread":false},{"title":"jtag_vpi_tb.v <span style='color:#111;'> 1.13KB </span>","children":null,"spread":false},{"title":"jtag_tap","children":[{"title":"jtag_tap.v <span style='color:#111;'> 20.53KB </span>","children":null,"spread":false}],"spread":true},{"title":"include","children":[{"title":"adbg_or1k_defines.v <span style='color:#111;'> 4.14KB </span>","children":null,"spread":false},{"title":"adbg_wb_defines.v <span style='color:#111;'> 4.42KB </span>","children":null,"spread":false},{"title":"adbg_defines.v <span style='color:#111;'> 3.68KB </span>","children":null,"spread":false},{"title":"tap_defines.v <span style='color:#111;'> 3.47KB </span>","children":null,"spread":false}],"spread":true},{"title":"jtag_soc.v <span style='color:#111;'> 2.38KB </span>","children":null,"spread":false},{"title":"ram","children":[{"title":"ram_wb_b3.v <span style='color:#111;'> 6.07KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"verilator","children":[{"title":"tb.cpp <span style='color:#111;'> 1.10KB </span>","children":null,"spread":false}],"spread":true},{"title":"test_client.c <span style='color:#111;'> 9.28KB </span>","children":null,"spread":false}],"spread":true},{"title":".gitignore <span style='color:#111;'> 37B </span>","children":null,"spread":false},{"title":"README.md <span style='color:#111;'> 1.88KB </span>","children":null,"spread":false},{"title":"jtagServer.h <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"jtag_vpi.v <span style='color:#111;'> 5.01KB </span>","children":null,"spread":false},{"title":"jtag_vpi.c <span style='color:#111;'> 8.26KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]