FPGA实现多功能数字钟（Verilog）.rar

[{"title":"（ 16 个子文件 654KB ） FPGA实现多功能数字钟（Verilog）.rar","children":[{"title":"testbench","children":[{"title":"time_counter_tb.v.bak <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"key_module_tb.v <span style='color:#111;'> 3.13KB </span>","children":null,"spread":false},{"title":"adjust_module_tb.v <span style='color:#111;'> 5.39KB </span>","children":null,"spread":false},{"title":"digital_clock_top_tb.v <span style='color:#111;'> 4.24KB </span>","children":null,"spread":false},{"title":"time_counter_tb.v <span style='color:#111;'> 1.39KB </span>","children":null,"spread":false}],"spread":true},{"title":"work","children":[{"title":"led_seg7_display.v <span style='color:#111;'> 3.34KB </span>","children":null,"spread":false},{"title":"adjust_module.v <span style='color:#111;'> 12.16KB </span>","children":null,"spread":false},{"title":"digital_clock_top.v <span style='color:#111;'> 3.89KB </span>","children":null,"spread":false},{"title":"time_counter.v <span style='color:#111;'> 9.05KB </span>","children":null,"spread":false},{"title":"key_filter.v <span style='color:#111;'> 1.86KB </span>","children":null,"spread":false},{"title":"alarm_music.v <span style='color:#111;'> 4.34KB </span>","children":null,"spread":false},{"title":"model_change.v <span style='color:#111;'> 602B </span>","children":null,"spread":false},{"title":"stop_watch.v <span style='color:#111;'> 3.52KB </span>","children":null,"spread":false},{"title":"key_module.v <span style='color:#111;'> 3.49KB </span>","children":null,"spread":false},{"title":"clk_div.v <span style='color:#111;'> 939B </span>","children":null,"spread":false}],"spread":true},{"title":"音乐播放器20200527 - 副本.docx <span style='color:#111;'> 659.18KB </span>","children":null,"spread":false}],"spread":true}]