RapidIO : the embedded system interconnect

RapidIO - The Embedded System Interconnect brings together one essential volume on RapidIO interconnect technology, providing a major reference work for the evaluation and understanding of RapidIO. Covering essential aspects of the specification, it also answers most usage questions from both hardware and software engineers. It will also serve as a companion text to the specifications when developing or working with the RapidIO interconnect technology. Including the history of RapidIO and case of studies of RapidIO deployment, this really is the definitive reference guide for this new area of technology. Preface xix 1 The Interconnect Problem 1 1.1 Processor Performance and Bandwidth Growth 1 1.2 Multiprocessing 2 1.3 System of Systems 3 1.4 Problems with Traditional Buses 4 1.4.1 Bus Loading 6 1.4.2 Signal Skew 6 1.4.3 Expense of Wider Buses 6 1.4.4 Problems with PCI 7 1.5 The Market Problem 7 1.6 RapidIO: A New Approach 8 1.6.1 Why RapidIO? 8 1.7 Where Will it be Used? 9 1.8 An Analogy 11 References 12 2 RapidIO Technology 13 2.1 Philosophy 13 2.2 The Specification Hierarchy 14 2.3 RapidIO Protocol Overview 15 2.3.1 Packets and Control Symbols 15 2.4 Packet Format 16 2.5 Transaction Formats and Types 17 2.6 Message Passing 17 2.7 Globally Shared Memory 18 2.8 Future Extensions 18 2.9 Flow Control 18 2.9.1 Link Level Flow Control 18 2.9.2 End-to-end Flow Control 19 CONTENTS vi 2.10 The Parallel Physical Layer 20 2.10.1 Parallel Electrical Interface 21 2.11 The Serial Physical Layer 21 2.11.1 PCS and PMA Layers 21 2.11.2 Electrical Interface 22 2.12 Link Protocol 22 2.13 Maintenance and Error Management 23 2.13.1 Maintenance 23 2.13.2 System Discovery 23 2.13.3 Error Coverage 23 2.13.4 Error Recovery 24 2.14 Performance 24 2.14.1 Packet Structures 24 2.14.2 Source Routing and Concurrency 25 2.14.3 Packet Overhead 25 2.15 Operation Latency 25 References 26 3 Devices, Switches, Transactions and Operations 27 3.1 Processing Element Models 27 3.1.1 Integrated Processor