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xilinx AXI桥IP核使用说明文档，介绍AXI 桥的使用方法

由Intel公司出版的一本书，专用于高速的电路设计。包括高速设计的原理，信号完整性的模型，仿真相关。高速PCB设计等。该书都有较为具体的描述。

这是一本关于RapidIO互联的经典书籍。RapidIO是一种高速互联接口协议，适于高性能嵌入式系统中，用于GHz的数据传输。

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.

RapidIO - The Embedded System Interconnect brings together one essential volume on RapidIO interconnect technology, providing a major reference work for the evaluation and understanding of RapidIO. Covering essential aspects of the specification, it also answers most usage questions from both hardware and software engineers. It will also serve as a companion text to the specifications when developing or working with the RapidIO interconnect technology. Including the history of RapidIO and case of studies of RapidIO deployment, this really is the definitive reference guide for this new area of technology. Preface xix 1 The Interconnect Problem 1 1.1 Processor Performance and Bandwidth Growth 1 1.2 Multiprocessing 2 1.3 System of Systems 3 1.4 Problems with Traditional Buses 4 1.4.1 Bus Loading 6 1.4.2 Signal Skew 6 1.4.3 Expense of Wider Buses 6 1.4.4 Problems with PCI 7 1.5 The Market Problem 7 1.6 RapidIO: A New Approach 8 1.6.1 Why RapidIO? 8 1.7 Where Will it be Used? 9 1.8 An Analogy 11 References 12 2 RapidIO Technology 13 2.1 Philosophy 13 2.2 The Specification Hierarchy 14 2.3 RapidIO Protocol Overview 15 2.3.1 Packets and Control Symbols 15 2.4 Packet Format 16 2.5 Transaction Formats and Types 17 2.6 Message Passing 17 2.7 Globally Shared Memory 18 2.8 Future Extensions 18 2.9 Flow Control 18 2.9.1 Link Level Flow Control 18 2.9.2 End-to-end Flow Control 19 CONTENTS vi 2.10 The Parallel Physical Layer 20 2.10.1 Parallel Electrical Interface 21 2.11 The Serial Physical Layer 21 2.11.1 PCS and PMA Layers 21 2.11.2 Electrical Interface 22 2.12 Link Protocol 22 2.13 Maintenance and Error Management 23 2.13.1 Maintenance 23 2.13.2 System Discovery 23 2.13.3 Error Coverage 23 2.13.4 Error Recovery 24 2.14 Performance 24 2.14.1 Packet Structures 24 2.14.2 Source Routing and Concurrency 25 2.14.3 Packet Overhead 25 2.15 Operation Latency 25 References 26 3 Devices, Switches, Transactions and Operations 27 3.1 Processing Element Models 27 3.1.1 Integrated Processor

RH2288H告警

xilinx AXI4-Stream-interconnect 仿真testbench文件，包含 AXI4-Stream traffic generator文件，自定义随机帧长，随机报文等，仅供学习参考。

本标准适用于柔性材料印刷电路板结构（FMIC's），在设备或电器中作为柔性、柔性安装、刚性和多层刚柔复合应用的部件使用，有或没有加强剂和粘合剂材料。

片上互连对多处理器片上系统（MPSoC）设计范例提出了重大挑战，尤其是在大数据时代。 关于最新技术，基于交叉开关的互连方法对于基于FPGA的小规模异构MPSoC仍然有效。 本文提出了一种基于交叉开关的片上互连方案，称为CRAIS。 CRAIS利用微处理器和MPSoC中的知识产权（IF）内核之间的可重新配置纵横开关互连。 硬件互连可以在执行期间动态重新配置。 FPGA原型的经验结果表明，与最先进的StarNet方法相比，CRAIS可以实现超过7倍的加速，而它仅使用StarNet的21％-35％的硬件资源。