[{"title":"( 84 个子文件 159KB ) Verilog写的同时求50组数据最小值的程序","children":[{"title":"min","children":[{"title":"min.v.bak <span style='color:#111;'> 6.00KB </span>","children":null,"spread":false},{"title":"min.v <span style='color:#111;'> 6.00KB </span>","children":null,"spread":false},{"title":"db","children":[{"title":"prev_cmp_min.qmsg <span style='color:#111;'> 3.49KB </span>","children":null,"spread":false},{"title":"min.map.bpm <span style='color:#111;'> 4.29KB </span>","children":null,"spread":false},{"title":"min.cmp_merge.kpt <span style='color:#111;'> 340B </span>","children":null,"spread":false},{"title":"min.eda.qmsg <span style='color:#111;'> 2.27KB </span>","children":null,"spread":false},{"title":"min.rtlv_sg.cdb <span style='color:#111;'> 3.34KB </span>","children":null,"spread":false},{"title":"min.cmp.rdb <span style='color:#111;'> 4.59KB </span>","children":null,"spread":false},{"title":"min.rtlv_sg_swap.cdb <span style='color:#111;'> 178B </span>","children":null,"spread":false},{"title":"min.(0).cnf.hdb <span style='color:#111;'> 4.70KB </span>","children":null,"spread":false},{"title":"min.map.logdb <span style='color:#111;'> 4B </span>","children":null,"spread":false},{"title":"min.db_info <span style='color:#111;'> 137B </span>","children":null,"spread":false},{"title":"min.sgdiff.hdb <span style='color:#111;'> 11.61KB </span>","children":null,"spread":false},{"title":"min.sld_design_entry.sci <span style='color:#111;'> 154B </span>","children":null,"spread":false},{"title":"min.map.hdb <span style='color:#111;'> 10.91KB </span>","children":null,"spread":false},{"title":"min.hier_info <span style='color:#111;'> 16.30KB </span>","children":null,"spread":false},{"title":"min.map.kpt <span style='color:#111;'> 334B </span>","children":null,"spread":false},{"title":"min.cbx.xml <span style='color:#111;'> 85B </span>","children":null,"spread":false},{"title":"min.map.ecobp <span style='color:#111;'> 28B </span>","children":null,"spread":false},{"title":"min.lpc.html <span style='color:#111;'> 430B </span>","children":null,"spread":false},{"title":"min.lpc.rdb <span style='color:#111;'> 385B </span>","children":null,"spread":false},{"title":"min.map.qmsg <span style='color:#111;'> 170.92KB </span>","children":null,"spread":false},{"title":"min.tmw_info <span style='color:#111;'> 67B </span>","children":null,"spread":false},{"title":"min.pre_map.cdb <span style='color:#111;'> 3.44KB </span>","children":null,"spread":false},{"title":"min.sld_design_entry_dsc.sci <span style='color:#111;'> 154B </span>","children":null,"spread":false},{"title":"min.rtlv.hdb <span style='color:#111;'> 11.37KB </span>","children":null,"spread":false},{"title":"min.map_bb.cdb <span style='color:#111;'> 2.60KB </span>","children":null,"spread":false},{"title":"min.tis_db_list.ddb <span style='color:#111;'> 174B </span>","children":null,"spread":false},{"title":"min.hif <span style='color:#111;'> 729B </span>","children":null,"spread":false},{"title":"min.eco.cdb <span style='color:#111;'> 161B </span>","children":null,"spread":false},{"title":"prev_cmp_min.eda.qmsg <span style='color:#111;'> 2.27KB </span>","children":null,"spread":false},{"title":"prev_cmp_min.map.qmsg <span style='color:#111;'> 3.49KB </span>","children":null,"spread":false},{"title":"min.map_bb.hdb <span style='color:#111;'> 9.76KB </span>","children":null,"spread":false},{"title":"min.map_bb.logdb <span style='color:#111;'> 4B </span>","children":null,"spread":false},{"title":"min.(0).cnf.cdb <span style='color:#111;'> 3.63KB </span>","children":null,"spread":false},{"title":"min.pre_map.hdb <span style='color:#111;'> 11.40KB </span>","children":null,"spread":false},{"title":"min.map.cdb <span style='color:#111;'> 4.12KB </span>","children":null,"spread":false},{"title":"min.lpc.txt <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"min.sgdiff.cdb <span style='color:#111;'> 2.02KB </span>","children":null,"spread":false},{"title":"min.syn_hier_info <span style='color:#111;'> 0B </span>","children":null,"spread":false}],"spread":false},{"title":"min.qws <span style='color:#111;'> 993B </span>","children":null,"spread":false},{"title":"min.qpf <span style='color:#111;'> 1.23KB </span>","children":null,"spread":false},{"title":"min.map.rpt <span style='color:#111;'> 60.10KB </span>","children":null,"spread":false},{"title":"min.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"incremental_db","children":[{"title":"compiled_partitions","children":[{"title":"min.root_partition.map.dpi <span style='color:#111;'> 863B </span>","children":null,"spread":false},{"title":"min.root_partition.map.atm <span style='color:#111;'> 27.21KB </span>","children":null,"spread":false},{"title":"min.root_partition.map.kpt <span style='color:#111;'> 337B </span>","children":null,"spread":false},{"title":"min.root_partition.map.hdbx <span style='color:#111;'> 6.32KB </span>","children":null,"spread":false}],"spread":true},{"title":"README <span style='color:#111;'> 653B </span>","children":null,"spread":false}],"spread":true},{"title":"transcript <span style='color:#111;'> 96B </span>","children":null,"spread":false},{"title":"min.qsf <span style='color:#111;'> 3.46KB </span>","children":null,"spread":false},{"title":"min.eda.rpt <span style='color:#111;'> 2.49KB </span>","children":null,"spread":false},{"title":"min.map.summary <span style='color:#111;'> 447B </span>","children":null,"spread":false},{"title":"min.flow.rpt <span style='color:#111;'> 7.41KB </span>","children":null,"spread":false},{"title":"simulation","children":[{"title":"modelsim","children":[{"title":"min_run_msim_rtl_verilog.do.bak4 <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"msim_transcript <span style='color:#111;'> 1.83KB </span>","children":null,"spread":false},{"title":"min_run_msim_rtl_verilog.do.bak3 <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"rtl_work","children":[{"title":"min_vlg_tst","children":[{"title":"_primary.dbs <span style='color:#111;'> 5.17KB </span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'> 45.56KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 82B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 4.22KB </span>","children":null,"spread":false}],"spread":false},{"title":"min","children":[{"title":"_primary.dbs <span style='color:#111;'> 9.74KB </span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'> 41.33KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 3.26KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 3.22KB </span>","children":null,"spread":false}],"spread":false},{"title":"_info <span style='color:#111;'> 618B </span>","children":null,"spread":false},{"title":"_temp","children":null,"spread":false},{"title":"_vmake <span style='color:#111;'> 26B </span>","children":null,"spread":false}],"spread":false},{"title":"data_out.txt <span style='color:#111;'> 5B </span>","children":null,"spread":false},{"title":"min_run_msim_rtl_verilog.do <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"min_run_msim_rtl_verilog.do.bak6 <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"min_run_msim_rtl_verilog.do.bak7 <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 40.00KB </span>","children":null,"spread":false},{"title":"min.vt.bak <span style='color:#111;'> 5.84KB </span>","children":null,"spread":false},{"title":"min_run_msim_rtl_verilog.do.bak10 <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"min_run_msim_rtl_verilog.do.bak5 <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"modelsim.ini <span style='color:#111;'> 6.12KB </span>","children":null,"spread":false},{"title":"min_run_msim_rtl_verilog.do.bak9 <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"min_run_msim_rtl_verilog.do.bak1 <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"min_run_msim_rtl_verilog.do.bak <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"min.vt <span style='color:#111;'> 5.84KB </span>","children":null,"spread":false},{"title":"min_run_msim_rtl_verilog.do.bak8 <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"min_run_msim_rtl_verilog.do.bak2 <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"min_run_msim_rtl_verilog.do.bak11 <span style='color:#111;'> 523B </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"min_nativelink_simulation.rpt <span style='color:#111;'> 992B </span>","children":null,"spread":false}],"spread":false}],"spread":true}]