Verilog数字钟（自动计时+手动校时+倒计时+整点报时+LCD显示）附完整源代码、详细注释和word报告.zip

[{"title":"（ 69 个子文件 2.12MB ） Verilog数字钟（自动计时+手动校时+倒计时+整点报时+LCD显示）附完整源代码、详细注释和word报告.zip","children":[{"title":"报告.doc <span style='color:#111;'> 1.04MB </span>","children":null,"spread":false},{"title":"数字钟","children":[{"title":"clk.sof <span style='color:#111;'> 821.38KB </span>","children":null,"spread":false},{"title":"clk.vwf <span style='color:#111;'> 3.84KB </span>","children":null,"spread":false},{"title":"clk.flow.rpt <span style='color:#111;'> 4.20KB </span>","children":null,"spread":false},{"title":"clk.qws <span style='color:#111;'> 1.16KB </span>","children":null,"spread":false},{"title":"db","children":[{"title":"clk.cmp.tdb <span style='color:#111;'> 123.37KB </span>","children":null,"spread":false},{"title":"clk.rpp.qmsg <span style='color:#111;'> 1.55KB </span>","children":null,"spread":false},{"title":"clk.eco.cdb <span style='color:#111;'> 140B </span>","children":null,"spread":false},{"title":"clk.syn_hier_info <span style='color:#111;'> 0B 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