基于verilog的数字时钟设计

[{"title":"（ 427 个子文件 8MB ） 基于verilog的数字时钟设计","children":[{"title":"sel.v.bak <span style='color:#111;'> 258B </span>","children":null,"spread":false},{"title":"FreqDiv_1MS.v <span style='color:#111;'> 153B </span>","children":null,"spread":false},{"title":"lab4_top.v <span style='color:#111;'> 840B </span>","children":null,"spread":false},{"title":"FreqDiv.v <span style='color:#111;'> 516B </span>","children":null,"spread":false},{"title":"key_esk.v.bak <span style='color:#111;'> 279B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]