quartus II 四位串行加法器VHDL和逻辑图

[{"title":"（ 100 个子文件 350KB ） quartus II 四位串行加法器VHDL和逻辑图","children":[{"title":"fourBitA.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"fourBitA.map.rpt <span style='color:#111;'> 18.89KB </span>","children":null,"spread":false},{"title":"fourBitA.dpf <span style='color:#111;'> 239B </span>","children":null,"spread":false},{"title":"fourBitA.pof <span style='color:#111;'> 2.00MB </span>","children":null,"spread":false},{"title":"fourBitA.flow.rpt <span style='color:#111;'> 7.54KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]