[{"title":"( 54 个子文件 185KB ) Verilog编写的状态机设计的例子","children":[{"title":"状态机设计的例子","children":[{"title":"FSM.pof <span style='color:#111;'> 512.18KB </span>","children":null,"spread":false},{"title":"FSM.map.summary <span style='color:#111;'> 369B </span>","children":null,"spread":false},{"title":"db","children":[{"title":"FSM.cmp0.ddb <span style='color:#111;'> 46.97KB </span>","children":null,"spread":false},{"title":"FSM.map.hdb <span style='color:#111;'> 4.92KB </span>","children":null,"spread":false},{"title":"FSM.pre_map.cdb <span style='color:#111;'> 1.43KB </span>","children":null,"spread":false},{"title":"FSM.psp <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"FSM.(0).cnf.cdb <span style='color:#111;'> 1.28KB </span>","children":null,"spread":false},{"title":"FSM.dbp <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"FSM.map.logdb <span style='color:#111;'> 4B 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</span>","children":null,"spread":false},{"title":"FSM.db_info <span style='color:#111;'> 136B </span>","children":null,"spread":false},{"title":"FSM.cmp.logdb <span style='color:#111;'> 4B </span>","children":null,"spread":false},{"title":"FSM.sld_design_entry.sci <span style='color:#111;'> 134B </span>","children":null,"spread":false},{"title":"FSM.cbx.xml <span style='color:#111;'> 85B </span>","children":null,"spread":false},{"title":"FSM.syn_hier_info <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"FSM.sgdiff.cdb <span style='color:#111;'> 1.14KB </span>","children":null,"spread":false},{"title":"FSM.cmp.rdb <span style='color:#111;'> 13.95KB </span>","children":null,"spread":false},{"title":"FSM.fit.qmsg <span style='color:#111;'> 21.83KB </span>","children":null,"spread":false},{"title":"FSM.map.qmsg <span style='color:#111;'> 5.53KB </span>","children":null,"spread":false},{"title":"FSM.rtlv_sg_swap.cdb <span style='color:#111;'> 158B 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