FPGA纯verliog实现串口通信,串口回环

上传者: m0_51497090 | 上传时间: 2025-05-30 00:18:27 | 文件大小: 5.92MB | 文件类型: ZIP
本次主要设计串口通信,基于verliog实现,并且通过了板级验证,实现串口回环,FPGA首先接收串口助手发送过来的数据,FPGA接收到数据之后,将接收的数据原封不动发送回去,实现串口回环,同时也可以做相应的修改,实现纯发送和纯接收。 日常通信方式中主要分为串行通信和并行通信,并行通信通常情况下是由多个发送或接收数据线组成的,每根线传输一位或多位,传输速率较快,但成本较高,不适合用于长距离通信。而串行通信通常是数据发送或接收在一条数据线上,数据的每一位按特定的通信协议顺序传输,这种方法会减少使用成本,但传输速率较并行传输来说较慢。而串口通信协议数据串行通信,所以我们本次主要来讲解下串行通信。串口通信数据线包括TX和RX,TX用来发送,RX用来接收,连接为TX接RX,RX接TX。串口通信数据帧由起始位,数据位,奇偶校验位和停止位组成,起始位低电平有效,一次传输一个8位数据。 该代码在后续测试中发现一些小问题,就是但连续发送多个字节时,回环发送回去的数据总是间隔发送,也就是每两个字节会漏掉一个字节,不过当只发送一个字节时,没有这个问题存在,该问题目前还在排查中,后面会给予相应的解决方案。

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