[{"title":"( 11 个子文件 27KB ) Verilog的视频采集模块","children":[{"title":"vedio_capture","children":[{"title":"vp422_444_dup.v <span style='color:#111;'> 7.15KB </span>","children":null,"spread":false},{"title":"special_svga_timing_generation.v.bak <span style='color:#111;'> 15.32KB </span>","children":null,"spread":false},{"title":"line_buffer.v <span style='color:#111;'> 11.06KB </span>","children":null,"spread":false},{"title":"pipe_line_delay.v <span style='color:#111;'> 2.79KB </span>","children":null,"spread":false},{"title":"lf_decode.v <span style='color:#111;'> 9.03KB </span>","children":null,"spread":false},{"title":"ycrcb2rgb.v <span style='color:#111;'> 4.50KB </span>","children":null,"spread":false},{"title":"lf_decode.v.bak <span style='color:#111;'> 8.97KB </span>","children":null,"spread":false},{"title":"neg_edge_detect.v <span style='color:#111;'> 2.97KB </span>","children":null,"spread":false},{"title":"svga_defines.v <span style='color:#111;'> 7.67KB </span>","children":null,"spread":false},{"title":"video_capture.v <span style='color:#111;'> 13.57KB </span>","children":null,"spread":false},{"title":"special_svga_timing_generation.v <span style='color:#111;'> 15.32KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]