在MAX+PLUS II中,使用图形编辑器设计一个3位的十进制加法计数器,使用VHDL语言设计一个D触发器

上传者: bi_qianyu | 上传时间: 2019-12-25 11:10:27 | 文件大小: 164KB | 文件类型: rar
1.在图形编辑器中设计一个3位的十进制加法计数器,以xxxcnt3.gdf命名保存(‘xxx’为您的姓名拼音首字母)。器件设定为EPM7128LC84-6。要求能够从0计数到999。从999归零时产生一个高电平的报警信号。进行波形仿真,验证功能正确。分析此电路的最高计数频率。 2.修改这个计数器的归零值,使其计数到119就归零,增加异步清零功能,加法计数/减法计数控制功能。 3.在文本编辑器中使用VHDL语言设计一个D触发器,具有反向输出端。命名为xxxdff.vhd,仿真验证。

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评论信息

  • liusy780626 :
    很好的资源!谢谢楼主的分享!
    2018-10-13
  • liusy780626 :
    很好的资源!谢谢楼主的分享!
    2018-10-13
  • smgk :
    东西还行,收藏了。
    2015-02-06
  • smgk :
    东西还行,收藏了。
    2015-02-06
  • u014771464 :
    仿真效果貌似有问题啊,但是思路可取。
    2014-11-18
  • 云凌枫 :
    仿真效果貌似有问题啊,但是思路可取。
    2014-11-18
  • u012923937 :
    是自己需要的,值得学习
    2014-01-15
  • 小熊猫2 :
    是自己需要的,值得学习
    2014-01-15
  • u011228845 :
    仿真效果貌似有问题啊,但是思路可取
    2013-11-06
  • 浅墨殇 :
    仿真效果貌似有问题啊,但是思路可取
    2013-11-06

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