slave spi 接口verilog 代码包括testbanch

[{"title":"（ 127 个子文件 612KB ） slave spi 接口verilog 代码包括testbanch","children":[{"title":"vcs.log <span style='color:#111;'> 5.15KB </span>","children":null,"spread":false},{"title":"spi_mast.v <span style='color:#111;'> 3.11KB </span>","children":null,"spread":false},{"title":"register_file.v <span style='color:#111;'> 484B </span>","children":null,"spread":false},{"title":"tb_slave_spi.v <span style='color:#111;'> 2.66KB </span>","children":null,"spread":false},{"title":"tc1.v <span style='color:#111;'> 1.37KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]