Verilog实现MIPS的5级流水线cpu设计（Modelsim仿真）.rar

[{"title":"（ 19 个子文件 13KB ） Verilog实现MIPS的5级流水线cpu设计（Modelsim仿真）.rar","children":[{"title":"cpu","children":[{"title":"HILO.v <span style='color:#111;'> 811B </span>","children":null,"spread":false},{"title":"min_sopc.v <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"testBench.v <span style='color:#111;'> 331B </span>","children":null,"spread":false},{"title":"instructions.data <span style='color:#111;'> 148B </span>","children":null,"spread":false},{"title":"ID.v <span style='color:#111;'> 7.84KB </span>","children":null,"spread":false},{"title":"ID_EX.v <span style='color:#111;'> 1.63KB </span>","children":null,"spread":false},{"title":"ctrl.v <span style='color:#111;'> 387B </span>","children":null,"spread":false},{"title":"defines.v <span style='color:#111;'> 6.64KB </span>","children":null,"spread":false},{"title":"EX_MEM.v <span style='color:#111;'> 1.74KB </span>","children":null,"spread":false},{"title":"insMem.v <span style='color:#111;'> 786B </span>","children":null,"spread":false},{"title":"说明.txt <span style='color:#111;'> 114B </span>","children":null,"spread":false},{"title":"MEM_WB.v <span style='color:#111;'> 1.24KB </span>","children":null,"spread":false},{"title":"MEM.v <span style='color:#111;'> 1.84KB </span>","children":null,"spread":false},{"title":"pc.v <span style='color:#111;'> 789B </span>","children":null,"spread":false},{"title":"MIPS_32CPU.v <span style='color:#111;'> 8.51KB </span>","children":null,"spread":false},{"title":"RegFiles.v <span style='color:#111;'> 2.01KB </span>","children":null,"spread":false},{"title":"IF_ID.v <span style='color:#111;'> 646B </span>","children":null,"spread":false},{"title":"EX.v <span style='color:#111;'> 9.42KB </span>","children":null,"spread":false},{"title":"dataMem.v <span style='color:#111;'> 1.01KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]